Datasheet

Specifications
MC56F825x/MC56F824x Digital Signal Controller, Rev. 3
Freescale Semiconductor 67
Figure 29. Test Access Port Timing Diagram
7.23 Quad Timer Timing
Figure 30. Timer Timing
Table 39. Timer Timing
1, 2
1
In the formulas listed, T = the clock cycle. For 32 MHz operation, T = 31.25 ns.
2. Parameters listed are guaranteed by design.
Characteristic Symbol Min Max Unit See Figure
Timer input period P
IN
2T + 6 — ns Figure 30
Timer input high/low period P
INHL
1T + 3 — ns Figure 30
Timer output period P
OUT
125 — ns Figure 30
Timer output high/low period P
OUTHL
50 — ns Figure 30
Input Data Valid
Output Data Valid
t
DS
t
DH
t
DV
t
TS
TCK
(Input)
TDI
(Input)
TDO
(Output)
TDO
(Output)
TMS
P
OUT
P
OUTHL
P
OUTHL
P
IN
P
INHL
P
INHL
Timer Inputs
Timer Outputs