Datasheet

MC56F825x/MC56F824x Digital Signal Controller, Rev. 3
Specifications
Freescale Semiconductor66
Figure 27. Timing Definition for Standard Mode Devices on the I
2
C Bus
7.22 JTAG Timing
Figure 28. Test Clock Input Timing Diagram
Table 38. JTAG Timing
Characteristic Symbol Min Max Unit See Figure
TCK frequency of operation
1
1
TCK frequency of operation must be less than 1/8 the processor rate.
f
OP
DC SYS_CLK/8 MHz Figure 28
TCK clock pulse width t
PW
50 — ns Figure 28
TMS, TDI data set-up time t
DS
5—nsFigure 29
TMS, TDI data hold time t
DH
5—nsFigure 29
TCK low to TDO data valid t
DV
—30ns Figure 29
TCK low to TDO tri-state t
TS
—30ns Figure 29
SDA
SCL
t
HD; STA
t
HD; DAT
t
LOW
t
SU; DAT
t
HIGH
t
SU; STA
SR
P
S
S
t
HD; STA
t
SP
t
SU; STO
t
BUF
t
f
t
r
t
f
t
r
TCK
(Input)
V
M
V
IL
V
M
= V
IL
+ (V
IH
– V
IL
)/2
t
PW
1/f
OP
t
PW
V
M
V
IH