Datasheet

Specifications
MC56F825x/MC56F824x Digital Signal Controller, Rev. 3
Freescale Semiconductor 65
7.20 Freescale’s Scalable Controller Area Network (MSCAN)
Figure 26. Bus Wake-up Detection
7.21 Inter-Integrated Circuit Interface (I
2
C) Timing
Table 36. MSCAN Timing
Characteristic Symbol Min Max Unit
Baud Rate BR
CAN
— 1 Mbps
Bus Wake-up detection T
WAKEUP
T
IPBUS
— μs
Table 37. I
2
C Timing
Characteristic Symbol
Standard Mode
Unit
Minimum Maximum
SCL Clock Frequency f
SCL
0 100 kHz
Hold time (repeated) START condition. After this period, the first
clock pulse is generated.
t
HD; STA
4.0 — μs
LOW period of the SCL clock t
LOW
4.7 — μs
HIGH period of the SCL clock t
HIGH
4.0 — μs
Set-up time for a repeated START condition t
SU; STA
4.7 — μs
Data hold time for I
2
C bus devices t
HD; DAT
0
1
1
The master mode I
2
C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
acknowledge this address byte, a negative hold time can result, depending on the edge rates of the SDA and SCL lines.
3.45
2
2
The maximum t
HD; DAT
must be met only if the device does not stretch the LOW period (t
LOW
) of the SCL signal.
μs
Data set-up time t
SU; DAT
250
3
3
A Fast mode I
2
C bus device can be used in a Standard mode I
2
C bus system, but the requirement t
SU; DAT
> = 250 ns must
then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device
does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
t
rmax
+ t
SU; DAT
= 1000 + 250 = 1250 ns (according to the Standard mode I
2
C bus specification) before the SCL line is released.
—ns
Rise time of SDA and SCL signals t
r
— 1000 ns
Fall time of SDA and SCL signals t
f
— 300 ns
Set-up time for STOP condition t
SU; STO
4.0 — μs
Bus free time between STOP and START condition t
BUF
4.7 — μs
Pulse width of spikes that must be suppressed by the input filter t
SP
N/A N/A ns
T
WAKEUP
MSCAN_RX
CAN receive
data pin
(Input)