Datasheet

Specifications
MC56F825x/MC56F824x Digital Signal Controller, Rev. 3
Freescale Semiconductor 61
Data set-up time required for inputs
Master
Slave
t
DS
20
0
—
—
ns
ns
Figure 20,
Figure 21,
Figure 22,
Figure 23
Data hold time required for inputs
Master
Slave
t
DH
0
2
—
—
ns
ns
Figure 20,
Figure 21,
Figure 22,
Figure 23
Access time (time to data active from high-impedance state)
Slave
t
A
4.8 15 ns
Figure 23
Disable time (hold time to high-impedance state)
Slave
t
D
3.7 15.2 ns
Figure 23
Data valid for outputs
Master
Slave (after enable edge)
t
DV
—
—
4.5
20.4
ns
ns
Figure 20,
Figure 21,
Figure 22,
Figure 23
Data invalid
Master
Slave
t
DI
0
0
—
—
ns
ns
Figure 20,
Figure 21,
Figure 22,
Figure 23
Rise time
Master
Slave
t
R
—
—
11.5
10.0
ns
ns
Figure 20,
Figure 21,
Figure 22,
Figure 23
Fall time
Master
Slave
t
F
—
—
9.7
9.0
ns
ns
Figure 20,
Figure 21,
Figure 22,
Figure 23
1
Parameters listed are guaranteed by design.
Table 34. SPI Timing
1
(continued)
Characteristic Symbol Min Max Unit Refer to