Datasheet

MC56F825x/MC56F824x Digital Signal Controller, Rev. 3
Specifications
Freescale Semiconductor60
7.17 Reset, Stop, Wait, Mode Select, and Interrupt Timing
NOTE
All address and data buses described here are internal.
Figure 19. GPIO Interrupt Timing (Negative Edge-Sensitive)
7.18 Queued Serial Peripheral Interface (SPI) Timing
Table 33. Reset, Stop, Wait, Mode Select, and Interrupt Timing
1,2
1
In the formulas, T = system clock cycle and T
osc
= oscillator clock cycle. For an operating frequency of 32 MHz, T = 31.25 ns.
At 4 MHz (used coming out of reset and stop modes), T = 250 ns.
2
Parameters listed are guaranteed by design.
Characteristic Symbol Typical Min Typical Max Unit See Figure
Minimum RESET Assertion Duration
3
3
This minimum number guarantees that a reliable reset occurs.
t
RA
4T — ns —
Minimum GPIO pin Assertion for Interrupt t
IW
2T — ns Figure 19
RESET
deassertion to First Address Fetch t
RDA
96T
OSC
+ 64T 97T
OSC
+ 65T ns —
Delay from Interrupt Assertion to Fetch of first
instruction (exiting Stop)
t
IF
—6Tns—
Table 34. SPI Timing
1
Characteristic Symbol Min Max Unit Refer to
Cycle time
Master
Slave
t
C
125
62.5
—
—
ns
ns
Figure 20,
Figure 21,
Figure 22,
Figure 23
Enable lead time
Master
Slave
t
ELD
—
31
—
—
ns
ns
Figure 23
Enable lag time
Master
Slave
t
ELG
—
125
—
—
ns
ns
Figure 23
Clock (SCK) high time
Master
Slave
t
CH
50
31
—
—
ns
ns
Figure 20,
Figure 21,
Figure 22,
Figure 23
Clock (SCK) low time
Master
Slave
t
CL
50
31
—
—
ns
ns
Figure 23
GPIO pin
(Input)
t
IW