Datasheet

MC56F825x/MC56F824x Digital Signal Controller, Rev. 3
Specifications
Freescale Semiconductor58
Figure 17. External Clock Timing
7.14 Phase Locked Loop Timing
External clock input rise time
4
t
rise
—— 3ns
External clock input fall time
5
t
fall
—— 3ns
Input high voltage overdrive by an external clock V
ih
0.85V
DD
——V
Input high voltage overdrive by an external clock V
il
——0.3V
DD
V
1
Parameters listed are guaranteed by design.
2
See Figure 17 for details on using the recommended connection of an external clock driver.
3
The chip may not function if the high or low pulse width is smaller than 6.25 ns.
4
External clock input rise time is measured from 10% to 90%.
5
External clock input fall time is measured from 90% to 10%.
Table 30. Phase Locked Loop Timing
Characteristic Symbol Min Typ Max Unit
PLL input reference frequency
1
1
An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly. The
PLL is optimized for 8 MHz input.
f
ref
488 MHz
PLL output frequency
2
2
The core system clock operates at 1/6 of the PLL output frequency.
f
op
120 — 240 MHz
PLL lock time
3 4
3
This is the time required after the PLL is enabled to ensure reliable operation.
4
From powerdown to powerup state at 60 MHz system clock state.
t
plls
—40100µs
Accumulated jitter using an 8 MHz external crystal as the PLL source
5
5
This is measured on the CLKO signal (programmed as system clock) over 264 system clocks at 60 MHz system clock
frequency and using an 8 MHz oscillator frequency.
J
A
——TBD%
Cycle-to-cycle jitter t
jitterpll
—350— ps
Table 29. External Clock Operation Timing Requirements
1
(continued)
Characteristic Symbol Min Typ Max Unit
90%
50%
10%
90%
50%
10%
External
Clock
t
PW
t
PW
t
fall
t
rise
V
IL
V
IH
Note: The midpoint is V
IL
+ (V
IH
– V
IL
)/2.