Datasheet

Specifications
MC56F825x/MC56F824x Digital Signal Controller, Rev. 3
Freescale Semiconductor 57
Figure 16 shows the definitions of the following signal states:
• Active state, when a bus or signal is driven, and enters a low impedance state
• Tri-stated, when a bus or signal is placed in a high impedance state
• Data Valid state, when a signal level has reached V
OL
or V
OH
• Data Invalid state, when a signal level is in transition between V
OL
and V
OH
Figure 16. Signal States
7.11 Enhanced Flex PWM Characteristics
7.12 Flash Memory Characteristics
7.13 External Clock Operation Timing
Table 27. Enhanced Flex PWM Timing Parameters
Characteristic Symbol Min Typ Max Unit
NanoEdge Placement (NEP) step size
1 2 3
1
Required: IP bus clock is between 50 MHz and ~60 Mhz in NanoEdge Placement mode.
2
NanoEdge Placement step size is a function of clock frequency only. Temperature and voltage variations do not affect
NanoEdge Placement step size.
3
In NanoEdge Placement mode, the minimum pulse edge-to-edge cannot be less than 4 PWM clock cycles.
— — 521 — ps
Delay for fault input activating to PWM output deactivated — 1 — ns
Table 28. Flash Timing Parameters
Characteristic Symbol Min Typ Max Unit
Program time
1
1
Additional overhead is part of the programming sequence. Refer to the device’s reference manual for details.
tprog 20 — 40 μs
Erase time
2
2
Specifies page erase time. There are 1024 bytes per page in the program flash memory.
terase 20 — — ms
Mass erase time
tme 100 — — ms
Table 29. External Clock Operation Timing Requirements
1
Characteristic Symbol Min Typ Max Unit
Frequency of operation (external clock driver)
2
f
osc
——120 MHz
Clock pulse width
3
t
PW
6.25 — — ns
Data Invalid State
Data1
Data3 Valid
Data2 Data3
Data1 Valid
Data Active Data Active
Data2 Valid
Data
Three-stated