Datasheet

MC56F825x/MC56F824x Digital Signal Controller, Rev. 3
Specifications
Freescale Semiconductor50
7.3 ESD Protection and Latch-up Immunity
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits, use
normal handling precautions to avoid exposure to static discharge. Qualification tests are performed to ensure that these devices
can withstand exposure to reasonable levels of static without suffering any permanent damage.
All ESD testing conforms with AEC-Q100 Stress Test Qualification. During device qualification, ESD stresses are performed
for the human body model (HBM), the machine model (MM), and the charge device model (CDM).
All latch-up testing conforms with AEC-Q100 Stress Test Qualification.
A device is defined as a failure if, after exposure to ESD pulses, the device no longer meets the device specification.
Comprehensive DC parametric and functional testing is performed according to the applicable device specification at room
temperature and then at hot temperature, unless specified otherwise in the device specification.
7.4 Thermal Characteristics
This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power
dissipation on I/O pins is usually small compared to power dissipation in on-chip logic and voltage regulator circuits, and it is
user-determined rather than being controlled by the device design. To account for P
I/O
in power calculations, determine the
difference between actual pin voltage and V
SS
or V
DD
and multiply by the pin current for each I/O pin. Except in cases of
unusually high pin current (heavy loads), the difference between pin voltage and V
SS
or V
DD
is very small.
Table 18. MC56F825x/MC56F824x ESD/Latch-up Protection
Characteristic
1
1
Parameter is achieved by design characterization on a small sample size from typical devices under
typical conditions, unless otherwise noted
Min Typ Max Unit
ESD for Human Body Model (HBM) 2000 — — V
ESD for Machine Model (MM) 200 — — V
ESD for Charge Device Model (CDM) 750 — — V
Latch-up current at T
A
= 85
o
C (I
LAT
) ± 100 mA
Table 19. 44LQFP Package Thermal Characteristics
Characteristic Comments Symbol
Value
(LQFP)
Unit
Junction to ambient
Natural convection
Single layer board
(1s)
R
θJA
70 °C/W
Junction to ambient
Natural convection
Four layer board
(2s2p)
R
θJMA
48 °C/W
Junction to ambient
(@200 ft/min)
Single layer board
(1s)
R
θJMA
57 °C/W
Junction to ambient
(@200 ft/min)
Four layer board
(2s2p)
R
θJMA
42 °C/W
Junction to board R
θJB
30 °C/W
Junction to case R
θJC
13 °C/W
Junction to package top Natural convection Ψ
JT
2°C/W