Datasheet

MC56F825x/MC56F824x Digital Signal Controller, Rev. 3
General System Control Information
Freescale Semiconductor36
5 General System Control Information
5.1 Overview
This section discusses power pins, reset sources, interrupt sources, clock sources, the system integration module (SIM), ADC
synchronization, and JTAG/EOnCE interfaces.
5.2 Power Pins
V
DD
, V
SS
and V
DDA
, V
SSA
are the primary power supply pins for the device. The voltage source supplies power to all on-chip
peripherals, I/O buffer circuitry, and internal voltage regulators. The device has multiple internal voltages to provide regulated
lower-voltage sources for the peripherals, core, memory, and on-chip relaxation oscillators.
Typically, at least two separate capacitors are across the power pins to bypass the glitches and provide bulk charge storage. In
this case, a bulk electrolytic or tantalum capacitor, such as a 10 µF tantalum capacitor, should provide bulk charge storage for
the overall system, and a 0.1 µF ceramic bypass capacitor should be located as near to the device power pins as is practical to
suppress high-frequency noise. Each pin must have a bypass capacitor for optimal noise suppression.
V
DDA
and V
SSA
are the analog power supply pins for the device. This voltage source supplies power to the ADC, PGA, and
CMP modules. A 0.1 µF ceramic bypass capacitor should be located as near to the device V
DDA
and V
SSA
pins as is practical
to suppress high-frequency noise. V
DDA
and V
SSA
are also the voltage reference high and voltage reference low inputs,
respectively, for the ADC module.
5.3 Reset
Resetting the device provides a way to start processing from a known set of initial conditions. During reset, most control and
status registers are forced to initial values, and the program counter is loaded from the reset vector. On-chip peripheral modules
are disabled and I/O pins are initially configured at the reset status shown in Table 5 on page 18.
The MC56F825x/MC56F824x has the following sources for reset:
• Power-on reset (POR)
• Partial power-down reset (PPD)
• Low-voltage detect (LVD)
• External pin reset (EXTR)
• Computer operating properly loss of reference reset (COP_LOR)
• Computer operating properly time-out reset (COP_CPU)
X:0xFF FF91–X:0xFF FF90 OBMSK (32 bits) Breakpoint Unit Mask Register 2
X:0xFF FF8F Reserved
X:0xFF FF8E OBCNTR EOnCE Breakpoint Unit Counter
X:0xFF FF8D Reserved
X:0xFF FF8C Reserved
X:0xFF FF8B Reserved
X:0xFF FF8A OESCR External Signal Control Register
X:0xFF FF89 –X:0xFF FF00 Reserved
Table 13. EOnCE Memory Map
Address Register Abbreviation Register Name