Datasheet

Memory Maps
MC56F825x/MC56F824x Digital Signal Controller, Rev. 3
Freescale Semiconductor 35
4.6 EOnCE Memory Map
Control registers of the EOnCE are located at the top of data memory space. These locations are fixed by the 56800E core. These
registers can also be accessed through the JTAG port if flash security is not set. Table 13 lists all EOnCE registers necessary to
access or control the EOnCE.
Cyclic Redundancy Check Generator CRC X:0x00 F230
Comparator Voltage Reference A REFA X:0x00 F240
Comparator Voltage Reference B REFB X:0x00 F250
Comparator Voltage Reference C REFB X:0x00 F260
Enhanced Flex PWM Module eFlexPWM X:0x00 F300
Flash Memory Interface FM X:0x00 F400
Freescale Controller Area Network
1
MSCAN X:0x00 F440
1
The core must enable clocks to the Freescale Controller Area Network module prior to
accessing MSCAN addresses. For details, refer to the MSCAN chapter of the device’s
reference manual.
Table 13. EOnCE Memory Map
Address Register Abbreviation Register Name
X:0xFF FFFF OTX1/ORX1 Transmit Register Upper Word
Receive Register Upper Word
X:0xFF FFFE OTX/ORX
(32 bits)
Transmit Register
Receive Register
X:0xFF FFFD OTXRXSR Transmit and Receive Status and Control Register
X:0xFF FFFC OCLSR Core Lock/Unlock Status Register
X:0xFF FFFB– X:0xFF FFA1 Reserved
X:0xFF FFA0 OCR Control Register
X:0xFF FF9F–X:0xFF FF9E OSCNTR
(24 bits)
Instruction Step Counter
X:0xFF FF9D OSR Status Register
X:0xFF FF9C OBASE Peripheral Base Address Register
X:0xFF FF9B OTBCR Trace Buffer Control Register
X:0xFF FF9A OTBPR Trace Buffer Pointer Register
X:0xFF FF99–X:0xFF FF98 OTB
(21–24 bits/stage)
Trace Buffer Register Stages
X:0xFF FF97–X:0xFF FF96 OBCR
(24 bits)
Breakpoint Unit Control Register
X:0xFF FF95–X:0xFF FF94 OBAR1
(24 bits)
Breakpoint Unit Address Register 1
X:0xFF FF93–X:0xFF FF92 OBAR2 (32 bits) Breakpoint Unit Address Register 2
Table 12. Data Memory Peripheral Base Address Map Summary (continued)
Peripheral Prefix Base Address