Datasheet

MC56F825x/MC56F824x Digital Signal Controller, Rev. 3

Memory Maps

Freescale Semiconductor34

• The 56F824x’s startup address is located at 0x00 2000. The reset value of VBA is reset to a value of 0x0020 that

corresponds to the address 0x00 2000.

By default, the chip reset address and COP reset address correspond to vector 0 and 1 of the interrupt vector table. In these

instances, the first two locations in the vector table must contain branch or JMP instructions. All other entries must contain JSR

instructions.

Table 48 on page 85 provides the MC56F825x/MC56F824x’s interrupt table contents and interrupt priority structure.

4.5 Peripheral Memory-Mapped Registers

The locations of on-chip peripheral registers are part of the data memory map on the 56800E series. These locations may be

accessed with the same addressing modes used for ordinary data memory. However, all peripheral registers should be read or

written using word accesses only.

Table 12 summarizes the base addresses for the set of peripherals on the MC56F825x/MC56F824x devices. Peripherals are

listed in order of the base address.

Table 12. Data Memory Peripheral Base Address Map Summary

Peripheral Prefix Base Address

Quad Timer A TMRA X:0x00 F000

Quad Timer B TMRB X:0x00 F040

Analog-to-Digital Converter ADC X:0x00 F080

Interrupt Controller INTC X:0x00 F0C0

System Integration Module SIM X:0x00 F0E0

Crossbar module XBAR X:0x00 F100

Computer Operating Properly module COP X:0x00 F110

On-Chip Clock Synthesis module OCCS X:0x00 F120

Power Supervisor PS X:0x00 F130

GPIO Port A GPIOA X:0x00 F140

GPIO Port B GPIOB X:0x00 F150

GPIO Port C GPIOC X:0x00 F160

GPIO Port D GPIOD X:0x00 F170

GPIO Port E GPIOE X:0x00 F180

GPIO Port F GPIOF X:0x00 F190

12-bit Digital-to-Analog Converter DAC X:0x00 F1A0

Analog Comparator A CMPA X:0x00 F1B0

Analog Comparator B CMPB X:0x00 F1C0

Analog Comparator C CMPC X:0x00 F1D0

Queued Serial Communication Interface 0 QSCI0 X:0x00 F1E0

Queued Serial Communication Interface 1 QSCI1 X:0x00 F1F0

Queued Serial Peripheral Interface QSPI X:0x00 F200

Inter-Integrated Circuit 0 I

C0 X:0x00 F210

Inter-Integrated Circuit 1 I

C1 X:0x00 F220