Datasheet

Memory Maps
MC56F825x/MC56F824x Digital Signal Controller, Rev. 3
Freescale Semiconductor 31
4.3 Data Map
The MC56F825x/MC56F824x series contains dual access memory. It can be accessed from core primary data buses (XAB1,
CDBW, CDBR) and secondary data buses (XAB2, XDB2). Addresses in data memory are selected on the XAB1 and XAB2
buses. Byte, word, and long data transfers occur on the 32-bit CDBR and CDBW buses. A second 16-bit read operation can be
performed in parallel on the XDB2 bus.
Peripheral registers and on-chip JTAG/EOnCE controller registers are memory mapped into data memory access. A special
direct address mode is supported for accessing a first 64-location in data memory by using a single word instruction.
The data memory map appears in Table 10 and Table 11.
1
All addresses are 16-bit word addresses.
2
This RAM is shared with data space starting at address X: 0x00 0000. See Figure 7.
Table 9. Program Memory Map
1
for 56F8245/46 at Reset
1
All addresses are 16-bit word addresses.
Begin/End Address Memory Allocation
P: 0x1F FFFF
P: 0x00 8800
RESERVED
P: 0x00 8BFF
P: 0x00 8000
On-chip RAM
2
: 6 KB
2
This RAM is shared with data space starting at address X: 0x00 0000. See Figure 7.
P: 0x00 7FFF
P: 0x00 2000
• Internal program flash: 48 KB
• Interrupt vector table locates from 0x00 2000 to 0x00 2085
• COP reset address = 0x00 2002
• Boot location = 0x00 2000
P: 0x00 2000
P: 0x00 0000
RESERVED
Table 10. 56F8247 and 56F8255/56/57 Data Memory Map
1
1
All addresses are 16-bit word addresses.
Begin/End Address Memory Allocation
X:0xFF FFFF
X:0xFF FF00
EOnCE
256 locations allocated
X:0xFF FEFF
X:0x01 0000
RESERVED
X:0x00 FFFF
X:0x00 F000
On-chip peripherals
4096 locations allocated
X:0x00 EFFF
X:0x00 9000
RESERVED
X:0x00 8FFF
X:0x00 8000
On-chip data RAM alias
X:0x00 7FFF
X:0x00 1000
RESERVED
X:0x00 0FFF
X:0x00 0000
On-chip data RAM
8KB
2