Datasheet

MC56F825x/MC56F824x Digital Signal Controller, Rev. 3
Signal/Connection Descriptions
Freescale Semiconductor18
3.3 MC56F825x/MC56F824x Signal Pins
After reset, each pin is configured for its primary function (listed first). Any alternative functionality, shown in parentheses and
as italic, must be programmed via the GPIO module’s peripheral enable registers (GPIO_x_PER) and the SIM module’s GPIO
peripheral select (GPSx) registers.
Table 5. MC56F825x/MC56F824x Signal and Package Information
Signal
Name
44
LQFP
48
LQFP
64
LQFP
Type
State
During
Reset
Signal Description
V
DD
29 Supply Supply I/O Power — This pin supplies 3.3 V power to the chip I/O interface.
V
DD
29 32 44
V
DD
40 44 60
V
SS
20 22 30 Supply Supply I/O Ground — These pins provide ground for chip I/O interface.
V
SS
28 31 43
V
SS
41 45 61
V
DDA
13 15 22 Supply Supply Analog Power — This pin supplies 3.3 V power to the analog
modules. It must be connected to a clean analog power supply.
V
SSA
14 16 23 Supply Supply Analog Ground — This pin supplies an analog ground to the analog
modules. It must be connected to a clean power supply.
V
CAP
17 19 26 Supply Supply V
CAP
— Connect a bypass capacitor of 2.2 µF or greater between
this pin and V
SS
to stabilize the core voltage regulator output
required for proper device operation. See Section 8.2, “Electrical
Design Considerations,” on page 73.
V
CAP
39 43 57
TDI
(GPIOD0)
44 48 64 Input
Input/
Output
Input,
internal
pullup
enabled
Test Data Input — This input pin provides a serial input data stream
to the JTAG/EOnCE port. It is sampled on the rising edge of TCK
and has an on-chip pullup resistor.
Port D GPIO — This GPIO pin can be individually programmed as
an input or output pin.
After reset, the default state is TDI.
TDO
(GPIOD1)
42 46 62 Output
Input/
Output
Output Test Data Output — This tri-stateable output pin provides a serial
output data stream from the JTAG/EOnCE port. It is driven in the
shift-IR and shift-DR controller states, and changes on the falling
edge of TCK.
Port D GPIO — This GPIO pin can be individually programmed as
an input or output pin.
After reset, the default state is TDO.
TCK
(GPIOD2)
111 Input
Input/
Output
Input,
internal
pullup
enabled
Test Clock Input — This input pin provides a gated clock to
synchronize the test logic and shift serial data to the JTAG/EOnCE
port. The pin is connected internally to a pullup resistor. A
Schmitt-trigger input is used for noise immunity.
Port D GPIO — This GPIO pin can be individually programmed as
an input or output pin.
After reset, the default state is TCK