Datasheet

Features
MC56F825x/MC56F824x Product Brief, Rev. 2
Preliminary
Freescale Semiconductor 7
2.4.2 Memory
• Dual Harvard architecture that permits as many as three simultaneous accesses to program and data
memory
• 48 KB (24K  16) to 64 KB (32K  16) on-chip flash memory with 2048 bytes (1024  16) page
size
•6KB (3K 16) to 8 KB (4K  16) on-chip RAM that is byte-addressable
• EEPROM emulation capability using flash
• Support for 60 MHz program execution from both internal flash and RAM memories
• Flash security and protection that prevent unauthorized users from gaining access to the internal
flash
2.4.3 Interrupt controller
• Five interrupt priority levels
— Three user-programmable priority levels for each interrupt source:
–Level 0
–Level 1
–Level 2
— Unmaskable level 3 interrupts include:
– Illegal instruction
– Hardware stack overflow
– Misaligned data access
– SWI3 instruction
— Maskable level 3 interrupts include:
– EOnCE step counter
– EOnCE breakpoint unit
– EOnCE trace buffer
— Lowest-priority software interrupt: level LP
• Nested interrupts: higher priority level interrupt request can interrupt lower priority interrupt
subroutine
• Two programmable fast interrupts that can be assigned to any interrupt source
• Notification to system integration module (SIM) to restart clock out of wait and stop states
• Ability to relocate interrupt vector table
The masking of interrupt priority level is managed by the 56800E core.
2.4.4 Power-saving features
• Low-speed run, wait, and stop modes: as low as 781 Hz clock provided by OCCS and internal
ROSC