Datasheet

MC56F825x/MC56F824x Product Brief, Rev. 2
Preliminary
Features
Freescale Semiconductor6
• Cyclic redundancy check (CRC) generator
• Two high-speed queued serial communication interface (QSCI) modules with LIN slave
functionality
• Queued serial peripheral interface (QSPI) module
• Two SMBus-compatible inter-integrated circuit (I
2
C) ports
• Freescale’s scalable controller area network (MSCAN) 2.0 A/B module
• Two 16-bit quad timers (2  4 16-bit timers)
• Computer operating properly (COP) watchdog module
• On-chip relaxation oscillator: 8 MHz (400 kHz at standby mode)
• Crystal/resonator oscillator
• Integrated power-on reset (POR) and low-voltage interrupt (LVI) and brown-out reset module
• Inter-module crossbar connection
• Up to 54 GPIOs
• 44-pin LQFP, 48-pin LQFP, and 64-pin LQFP packages
• Single supply: 3.0 V to 3.6 V
2.4.1 Core
• Efficient 56800E digital signal processor (DSP) engine with dual Harvard architecture
— Three internal address buses
— Four internal data buses
• As many as 60 million instructions per second (MIPS) at 60 MHz core frequency
• 155 basic instructions in conjunction with up to 20 address modes
• 32-bit internal primary data buses supporting 8-bit, 16-bit, and 32-bit data movement, addition,
subtraction, and logical operation
• Single-cycle 16  16-bit parallel multiplier-accumulator (MAC)
• Four 36-bit accumulators, including extension bits
• 32-bit arithmetic and logic multi-bit shifter
• Parallel instruction set with unique DSP addressing modes
• Hardware DO and REP loops
• Instruction set supporting DSP and controller functions
• Controller-style addressing modes and instructions for compact code
• Efficient C compiler and local variable support
• Software subroutine and interrupt stack with depth limited only by memory
• JTAG/enhanced on-chip emulation (EOnCE) for unobtrusive, processor speed–independent,
real-time debugging