Datasheet

MC56F825x/MC56F824x Product Brief, Rev. 2
Preliminary
Features
Freescale Semiconductor4
2.2 Block diagram
Figure 3 is a simplified block diagram of the MC56F825x.
Queued serial peripheral interface (QSPI) 1
High-speed queued serial communications interface (QSCI)
1
2
Controller area network (MSCAN) 0 1
High-speed 16-bit multi-purpose timers (TMR)
2
8
Computer operating properly (COP) watchdog timer Yes
Integrated power-on reset and low voltage detection Yes
Phase-locked loop (PLL) Yes
8 MHz (400 kHz at standby mode) on-chip ROSC Yes
Crystal/resonator oscillator Yes
CrossbarInput pins 666666
Output pins 226226
General purpose I/O (GPIO)
3
35 39 54 35 39 54
IEEE 1149.1 Joint Test Action Group (JTAG) interface Yes
Enhanced on-chip emulator (EOnCE) Yes
Operating temperature range –40 °C to 105 °C
Package 44LQFP 48LQFP 64LQFP 44LQFP 48LQFP 64LQFP
NOTES:
1
Can be clocked by high-speed peripheral clock up to 120 MHz.
2
Can be clocked by high-speed peripheral clock up to 120 MHz.
3
Shared with other function pins.
Table 1. MC56F825x/MC56F824x device comparison (continued)
Feature 56F8245 56F8246 56F8247 56F8255 56F8256 56F8257