Datasheet

Features
MC56F825x/MC56F824x Product Brief, Rev. 2
Preliminary
Freescale Semiconductor 11
2.5.9 I
2
C
• Two inter-integrated circuit (I
2
C) ports
— Operation at up to 400 kbps
— Support for master and slave operation
— Support for 10-bit address mode and broadcasting mode
— Support for SMBus, version 2
2.5.10 MSCAN
• One Freescale Scalable Controller Area Network (MSCAN) module
— Fully compliant with CAN protocol version 2.0 A/B
— Support for standard and extended data frames
— Support for data rate up to 1 Mbps
— Five receive buffers and three transmit buffers
2.5.11 COP
• Computer operating properly (COP) watchdog timer capable of selecting different clock sources
— Programmable prescaler and time-out period
— Programmable wait, stop, and partial power-down mode operation
— Causes loss of reference reset 128 cycles after loss of reference clock to the PLL is detected
— Choice of three clock sources:
– On-chip relaxation oscillator
– External crystal oscillator/external clock source
– System clock (IP bus to 60 MHz)
2.5.12 PS
• Power supervisor (PS)
— On-chip linear regulator for digital and analog circuitry to lower cost and reduce noise
— Integrated low-voltage detection to generate warning interrupt if V
DD
is below low-voltage
detection (LVI) threshold
— Integrated power-on reset (POR)
– Reliable reset process during power-on procedure
– POR is released after V
DD
passes low voltage detection (LVI) threshold
— Integrated brown-out reset
— Run, wait, and stop modes