Datasheet

MC56F825x/MC56F824x Product Brief, Rev. 2
Preliminary
Features
Freescale Semiconductor10
2.5.5 DAC
• One 12-bit digital-to-analog converter (12-bit DAC)
— 12-bit resolution
— Power-down mode
— Output can be routed to internal comparator or off chip
2.5.6 TMR
• Two four-channel 16-bit multi-purpose timer (TMR) modules
— Four independent 16-bit counter/timers with cascading capability per module
— Up to 120 MHz operating clock
— Each timer has capture and compare and quadrature decoder capability
— Up to twelve operating modes
— Four external inputs and two external outputs
2.5.7 QSCI
• Two queued serial communication interface (QSCI) modules with LIN slave functionality
— Up to 120 MHz operating clock
— Four-byte-deep FIFOs available on both transmit and receive buffers
— Full-duplex or single-wire operation
— Programmable 8- or 9-bit data format
— 13-bit integer and 3-bit fractional baud rate selection
— Two receiver wakeup methods:
– Idle line
– Address mark
— 1/16 bit-time noise detection
— LIN slave operation
2.5.8 QSPI
• One queued serial peripheral interface (QSPI) module
— Full-duplex operation
— Four-word deep FIFOs available on both transmit and receive buffers
— Master and slave modes
— Programmable length transactions (2–16 bits)
— Programmable transmit and receive shift order (MSB as first or last bit transmitted)
— Maximum slave module frequency = module clock frequency divided by two
— 13-bit baud rate divider for low-speed communication