Datasheet

Register Descriptions
56F8037/56F8027 Data Sheet, Rev. 8
Freescale Semiconductor 89
5.6.13.1 Fast Interrupt 1 Vector Address Low (FIVAL1)—Bits 15–0
The lower 16 bits of the vector address used for Fast Interrupt 1. This register is combined with FIVAH1
to form the 21-bit vector address for Fast Interrupt 1 defined in the FIM1 register.
5.6.14 Fast Interrupt 1 Vector Address High (FIVAH1)
Figure 5-16 Fast Interrupt 1 Vector Address High Register (FIVAH1)
5.6.14.1 Reserved—Bits 15–5
This bit field is reserved. Each bit must be set to 0.
5.6.14.2 Fast Interrupt 1 Vector Address High (FIVAH1)—Bits 4–0
The upper five bits of the vector address used for Fast Interrupt 1. This register is combined with FIVAL1
to form the 21-bit vector address for Fast Interrupt 1 defined in the FIM1 register.
5.6.15 IRQ Pending Register 0 (IRQP0)
Figure 5-17 IRQ Pending Register 0 (IRQP0)
5.6.15.1 IRQ Pending (PENDING)—Bits 16–2
This register bit values represent the pending IRQs for interrupt vector numbers 2 through 16. Ascending
IRQ numbers correspond to ascending bit locations.
• 0 = IRQ pending for this vector number
• 1 = No IRQ pending for this vector number
5.6.15.2 Reserved—Bit 0
This bit field is reserved. It must be set to 0.
Base + $D
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
0 0 0 0 0 0 0 0 0 0 0
FAST INTERRUPT 1 VECTOR
ADDRESS HIGH
Write
RESET
0000000000000000
Base + $E
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
PENDING[16:2] 1
Write
RESET
1111111111111111