Datasheet

Register Descriptions
56F8037/56F8027 Data Sheet, Rev. 8
Freescale Semiconductor 79
5.6.4 Interrupt Priority Register 3 (IPR3)
Figure 5-6 Interrupt Priority Register 3 (IPR3)
5.6.4.1 I
2
C Error Interrupt Priority Level (I2C_ERR IPL)—Bits 15–14
This field is used to set the interrupt priority level for the I
2
C Error IRQ. This IRQ is limited to priorities
0 through 2. It is disabled by default.
• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2
5.6.4.2 QSCI 1 Receiver Full Interrupt Priority Level (QSCI1_RCV IPL)—
Bits 13–12
This field is used to set the interrupt priority level for the QSCI1 Receiver Full IRQ. This IRQ is limited
to priorities 0 through 2. It is disabled by default.
• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2
5.6.4.3 QSCI 1 Receiver Error Interrupt Priority Level (QSCI1_RERR IPL)—
Bits 11–10
This field is used to set the interrupt priority level for the QSCI1 Receiver Error IRQ. This IRQ is limited
to priorities 0 through 2. It is disabled by default.
• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2
5.6.4.4 QSCI 1 Transmitter Idle Interrupt Priority Level (QSCI1_TIDL IPL)—
Bits 9–8
This field is used to set the interrupt priority level for the QSCI1 Transmitter Idle IRQ. This IRQ is limited
to priorities 0 through 2. It is disabled by default.
• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
Base + $3
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
I2C_ERR IPL
QSCI1_RCV
IPL
QSCI1_RER
R IPL
QSCI1_TIDL
IPL
QSCI1_XMIT
IPL
QSCI0_RCV
IPL
QSCI0_RERR
IPL
QSCI0_TIDL
IPL
Write
RESET
0 00000000000 0 0 00