Datasheet

Register Descriptions
56F8037/56F8027 Data Sheet, Rev. 8
Freescale Semiconductor 77
5.6.3 Interrupt Priority Register 2 (IPR2)
Figure 5-5 Interrupt Priority Register 2 (IPR2)
5.6.3.1 QSCI 0 Transmitter Empty Interrupt Priority Level (QSCI0_XMIT IPL)—
Bits 15–14
This field is used to set the interrupt priority level for the QSCI0 Transmitter Empty IRQ. This IRQ is
limited to priorities 0 through 2. It is disabled by default.
• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2
5.6.3.2 QSPI 1 Transmitter Empty Interrupt Priority Level (QSPI1_XMIT IPL)—
Bits 13–12
This field is used to set the interrupt priority level for the QSPI1 Transmitter Empty IRQ. This IRQ is
limited to priorities 0 through 2. It is disabled by default.
• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2
5.6.3.3 QSPI 1 Receiver Full Interrupt Priority Level (QSPI1_RCV IPL)—
Bits 11–10
This field is used to set the interrupt priority level for the QSPI1 Receiver Full IRQ. This IRQ is limited
to priorities 0 through 2. It is disabled by default.
• 00 = IRQ disabled (default)
• 01 = IRQ is priority level 0
• 10 = IRQ is priority level 1
• 11 = IRQ is priority level 2
5.6.3.4 QSPI 0 Transmitter Empty Interrupt Priority Level (QSPI0_XMIT IPL)—
Bits 9–8
This field is used to set the interrupt priority level for the QSPI0 Transmitter Empty IRQ. This IRQ is
limited to priorities 0 through 2. It is disabled by default.
Base + $2
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
QSCI0_XMIT
IPL
QSPI1_XMIT
IPL
QSPI1_RCV
IPL
QSPI0_XMIT
IPL
QSPI0_RCV
IPL
GPIOA IPL GPIOB IPL GPIOC IPL
Write
RESET
0000000000000000