Datasheet

56F8037/56F8027 Data Sheet, Rev. 8

66 Freescale Semiconductor

Table 4-34 Flash Module Registers Address Map

(FM_BASE = $00 F400)

FM_CLKDIV $0 Clock Divider Register

FM_CNFG $1 Configuration Register

$2 Reserved

FM_SECHI $3 Security High Half Register

FM_SECLO $4 Security Low Half Register

$5 - $9 Reserved

FM_PROT $10 Protection Register

$11 - $12 Reserved

FM_USTAT $13 User Status Register

FM_CMD $14 Command Register

$15 - $17 Reserved

FM_DATA $18 Data Buffer Register

$19 - $A Reserved

FM_OPT1 $1B Information Option Register 1

$1C Reserved

FM_TSTSIG $1D Test Array Signature Register

Table 4-35 MSCAN Registers Address Map

(MSCAN_BASE = $00 F800)

MSCAN_CTRL0 $00 Control Register 0

MSCAN_CTRL1 $01 Control Register 1

MSCAN_BTR0 $02 Bus Timing Register 0

MSCAN_BTR1 $03 Bus Timing Register 1

MSCAN_RFLG $04 Receiver Flag Register

MSCAN_RIER $05 Receiver Interrupt Enable Register

MSCAN_TFLG $06 Transmitter Flag Register

MSCAN_TIER $07 Transmitter Interrupt Enable Register

MSCAN_TARQ $08 Transmitter Message Abort Request Register

MSCAN_TAAK $09 Transmitter Message Abort Acknowledge Register

MSCAN_TBSEL $0A Transmitter Buffer Selection Register

MSCAN_IDAC $0B Identifier Acceptance Control Register

Reserved

MSCAN_MISC $0D Miscellaneous Register

MSCAN_RXERR $0E Receive Error Register

MSCAN_TXERR $0F Transmit Error Register