Datasheet

Peripheral Memory-Mapped Registers

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor 65

QSPI1_DELAY $5 Delay Register

Table 4-33 I

C Registers Address Map

(I2C_BASE = $00 F280)

I2C_CTRL $0 Control Register

I2C_TAR $2 Target Address Register

I2C_SAR $4 Slave Address Register

I2C_DATA $8 RX/TX Data Buffer and Command Register

I2C_SSHCNT $A Standard Speed Clock SCL High Count Register

I2C_SSLCNT $C Standard Speed Clock SCL Low Count Register

I2C_FSHCNT $E Fast Speed Clock SCL High Count Register

I2C_FSLCNT $10 Fast Speed Clock SCL Low Count Register

I2C_ISTAT $16 Interrupt Status Register

I2C_IMASK $18 Interrupt Mask Register

I2C_RISTAT $1A Raw Interrupt Status Register

I2C_RXFT $1C Receive FIFO Threshold Register

I2C_TXFT $1E Transmit FIFO Threshold Register

I2C_CLRINT $20 Clear Combined and Individual Interrupts Register

I2C_CLRRXUND $22 Clear RX_UNDER Interrupt Register

I2C_CLRRXOVR $24 Clear RX_OVER Interrupt Register

I2C_CLRTXOVR $26 Clear TX_OVER Interrupt Register

I2C_CLRRDREQ $28 Clear RD_REQ Interrupt Register

I2C_CLRTXABRT $2A Clear TX_ABRT Interrupt Register

I2C_CLRRXDONE $2C Clear RX_DONE Interrupt Register

I2C_CLRACT $2E Clear Activity Interrupt Register

I2C_CLRSTPDET $30 Clear STOP_DET Interrupt Register

I2C_CLRSTDET $32 Clear START_DET Interrupt Register

I2C_CLRGC $34 Clear GEN_CALL Interrupt Register

I2C_ENBL $36 Enable Register

I2C_STAT $38 Status Register

I2C_TXFLR $3A Transmit FIFO Level Register

I2C_RXFLR $3C Receive FIFO Level Register

I2C_TXABRTSRC $40 Transmit Abort Status Register

Table 4-32 Queued Serial Peripheral Interface 1 Registers Address Map

(QSPI1_BASE = $00 F230)