Datasheet

56F8037/56F8027 Data Sheet, Rev. 8

64 Freescale Semiconductor

Table 4-29 Queued Serial Communication Interface 0 Registers Address Map

(QSCI0_BASE = $00 F200)

QSCI0_RATE $0 Baud Rate Register

QSCI0_CTRL1 $1 Control Register 1

QSCI0_CTRL2 $2 Control Register 2

QSCI0_STAT $3 Status Register

QSCI0_DATA $4 Data Register

Table 4-30 Queued Serial Communication Interface 1 Registers Address Map

(QSCI1_BASE = $00 F210)

QSCI1_RATE $0 Baud Rate Register

QSCI1_CTRL1 $1 Control Register 1

QSCI1_CTRL2 $2 Control Register 2

QSCI1_STAT $3 Status Register

QSCI1_DATA $4 Data Register

Table 4-31 Queued Serial Peripheral Interface 0 Registers Address Map

(QSPI0_BASE = $00 F220)

QSPI0_SCTRL $0 Status and Control Register

QSPI0_DSCTRL $1 Data Size and Control Register

QSPI0_DRCV $2 Data Receive Register

QSPI0_DXMIT $3 Data Transmit Register

QSPI0_FIFO $4 FIFO Control Register

QSPI0_DELAY $5 Delay Register

Table 4-32 Queued Serial Peripheral Interface 1 Registers Address Map

(QSPI1_BASE = $00 F230)

QSPI1_SCTRL $0 Status and Control Register

QSPI1_DSCTRL $1 Data Size and Control Register

QSPI1_DRCV $2 Data Receive Register

QSPI1_DXMIT $3 Data Transmit Register

QSPI1_FIFO $4 FIFO Control Register