Datasheet
56F8037/56F8027 Data Sheet, Rev. 8
58 Freescale Semiconductor
PWM_DTIM1 $D Dead Time Register 1
PWM_DMAP1 $E Disable Mapping Register 1
PWM_DMAP2 $F Disable Mapping Register 2
PWM_CNFG $10 Configure Register
PWM_CCTRL $11 Channel Control Register
PWM_PORT $12 Port Register
PWM_ICCTRL $13 Internal Correction Control Register
PWM_SCTRL $14 Source Control Register
PWM_SYNC $15 Synchronization Window Register
PWM_FFILT0 $16 Fault0 Filter Register
PWM_FFILT1 $17 Fault1 Filter Register
PWM_FFILT2 $18 Fault2 Filter Register
PWM_FFILT3 $19 Fault3 Filter Register
Table 4-13 Interrupt Control Registers Address Map
(ITCN_BASE = $00 F0E0)
Register Acronym Address Offset Register Description
ITCN_IPR0 $0 Interrupt Priority Register 0
ITCN_IPR1 $1 Interrupt Priority Register 1
ITCN_IPR2 $2 Interrupt Priority Register 2
ITCN_IPR3 $3 Interrupt Priority Register 3
ITCN_IPR4 $4 Interrupt Priority Register 4
ITCN_IPR5 $5 Interrupt Priority Register 5
ITCN_IPR6 $6 Interrupt Priority Register 6
ITCN_VBA $7 Vector Base Address Register
ITCN_FIM0 $8 Fast Interrupt Match 0 Register
ITCN_FIVAL0 $9 Fast Interrupt Vector Address Low 0 Register
ITCN_FIVAH0 $A Fast Interrupt Vector Address High 0 Register
ITCN_FIM1 $B Fast Interrupt Match 1 Register
ITCN_FIVAL1 $C Fast Interrupt Vector Address Low 1 Register
ITCN_FIVAH1 $D Fast Interrupt Vector Address High 1 Register
ITCN_IRQP0 $E IRQ Pending Register 0
ITCN_IRQP1 $F IRQ Pending Register 1
ITCN_IRQP2 $10 IRQ Pending Register 2
Table 4-12 Pulse Width Modulator Registers Address Map (Continued)
(PWM_BASE = $00 F0C0)
Register Acronym Address Offset Register Description