Datasheet

Peripheral Memory-Mapped Registers
56F8037/56F8027 Data Sheet, Rev. 8
Freescale Semiconductor 57
ADC_HILIM0 $24 High Limit Register 0
ADC_HILIM1 $25 High Limit Register 1
ADC_HILIM2 $26 High Limit Register 2
ADC_HILIM3 $27 High Limit Register 3
ADC_HILIM4 $28 High Limit Register 4
ADC_HILIM5 $29 High Limit Register 5
ADC_HILIM6 $2A High Limit Register 6
ADC_HILIM7 $2B High Limit Register 7
ADC_OFFST0 $2C Offset Register 0
ADC_OFFST1 $2D Offset Register 1
ADC_OFFST2 $2E Offset Register 2
ADC_OFFST3 $2F Offset Register 3
ADC_OFFST4 $30 Offset Register 4
ADC_OFFST5 $31 Offset Register 5
ADC_OFFST6 $32 Offset Register 6
ADC_OFFST7 $33 Offset Register 7
ADC_PWR $34 Power Control Register
ADC_CAL $35 Calibration Register
Reserved
Table 4-12 Pulse Width Modulator Registers Address Map
(PWM_BASE = $00 F0C0)
Register Acronym Address Offset Register Description
PWM_CTRL $0 Control Register
PWM_FCTRL $1 Fault Control Register
PWM_FLTACK $2 Fault Status Acknowledge Register
PWM_OUT $3 Output Control Register
PWM_CNTR $4 Counter Register
PWM_CMOD $5 Counter Modulo Register
PWM_VAL0 $6 Value Register 0
PWM_VAL1 $7 Value Register 1
PWM_VAL2 $8 Value Register 2
PWM_VAL3 $9 Value Register 3
PWM_VAL4 $A Value Register 4
PWM_VAL5 $B Value Register 5
PWM_DTIM0 $C Dead Time Register 0
Table 4-11 Analog-to-Digital Converter Registers Address Map (Continued)
(ADC_BASE = $00 F080)
Register Acronym Address Offset Register Description