Datasheet

Peripheral Memory-Mapped Registers
56F8037/56F8027 Data Sheet, Rev. 8
Freescale Semiconductor 53
Table 4-9 Quad Timer A Registers Address Map
(TMRA_BASE = $00 F000)
Register Acronym Address Offset Register Description
TMRA0_COMP1 $0 Compare Register 1
TMRA0_COMP2 $1 Compare Register 2
TMRA0_CAPT $2 Capture Register
TMRA0_LOAD $3 Load Register
TMRA0_HOLD $4 Hold Register
TMRA0_CNTR $5 Counter Register
TMRA0_CTRL $6 Control Register
TMRA0_SCTRL $7 Status and Control Register
TMRA0_CMPLD1 $8 Comparator Load Register 1
TMRA0_CMPLD2 $9 Comparator Load Register 2
TMRA0_CSCTRL $A Comparator Status and Control Register
TMRA0_FILT $B Input Filter Register
Reserved
TMRA0_ENBL $F Timer Channel Enable Register
TMRA1_COMP1 $10 Compare Register 1
TMRA1_COMP2 $11 Compare Register 2
TMRA1_CAPT $12 Capture Register
TMRA1_LOAD $13 Load Register
TMRA1_HOLD $14 Hold Register
TMRA1_CNTR $15 Counter Register
TMRA1_CTRL $16 Control Register
TMRA1_SCTRL $17 Status and Control Register
TMRA1_CMPLD1 $18 Comparator Load Register 1
TMRA1_CMPLD2 $19 Comparator Load Register 2
TMRA1_CSCTRL $1A Comparator Status and Control Register
TMRA1_FILT $1B Input Filter Register
Reserved
TMRA2_COMP1 $20 Compare Register 1
TMRA2_COMP2 $21 Compare Register 2
TMRA2_CAPT $22 Capture Register
TMRA2_LOAD $23 Load Register
TMRA2_HOLD $24 Hold Register
TMRA2_CNTR $25 Counter Register
TMRA2_CTRL $26 Control Register
TMRA2_SCTRL $27 Status and Control Register
TMRA2_CMPLD1 $28 Comparator Load Register 1