Datasheet

Peripheral Memory-Mapped Registers
56F8037/56F8027 Data Sheet, Rev. 8
Freescale Semiconductor 51
4.6 Peripheral Memory-Mapped Registers
On-chip peripheral registers are part of the data memory map on the 56800E series. These locations may
be accessed with the same addressing modes used for ordinary Data memory, except all peripheral
registers should be read or written using word accesses only.
Table 4-8 summarizes base addresses for the set of peripherals on the 56F8037/56F8027 device.
Peripherals are listed in order of the base address.
The following tables list all of the peripheral registers required to control or access the peripherals.
X:$FF FF92 OBAR2 (32 bits) Breakpoint Unit Address Register 2
X:$FF FF91 Breakpoint Unit Mask Register 2
X:$FF FF90 OBMSK (32 bits) Breakpoint Unit Mask Register 2
X:$FF FF8F Reserved
X:$FF FF8E OBCNTR EOnCE Breakpoint Unit Counter
X:$FF FF8D Reserved
X:$FF FF8C Reserved
X:$FF FF8B Reserved
X:$FF FF8A OESCR External Signal Control Register
X:$FF FF89 - X:$FF FF00 Reserved
Table 4-8 Data Memory Peripheral Base Address Map Summary
Peripheral Prefix Base Address Table Number
Timer A TMRA X:$00 F000 4-9
Timer B TMRB X:$00 F040 4-10
ADC ADC X:$00 F080 4-11
PWM PWM X:$00 F0C0 4-12
ITCN ITCN X:$00 F0E0 4-13
SIM SIM X:$00 F100 4-14
COP COP X:$00 F120 4-15
CLK, PLL, OSC OCCS X:$00 F130 4-16
Power Supervisor PS X:$00 F140 4-17
GPIO Port A GPIOA X:$00 F150 4-18
GPIO Port B GPIOB X:$00 F160 4-19
GPIO Port C GPIOC X:$00 F170 4-20
GPIO Port D GPIOD X:$00 F180 4-21
PIT 0 PIT0 X:$00 F190 4-22
PIT 1 PIT1 X:$00 F1A0 4-23
PIT 2 PIT2 X:$00 F1B0 4-24
Table 4-7 EOnCE Memory Map (Continued)
Address Register Acronym Register Name