Datasheet

56F8037/56F8027 Data Sheet, Rev. 8
50 Freescale Semiconductor
Figure 4-2 Dual Port RAM for 56F8027
4.5 EOnCE Memory Map
Figure 4-7 lists all EOnCE registers necessary to access or control the EOnCE.
Table 4-7 EOnCE Memory Map
Address Register Acronym Register Name
X:$FF FFFF OTX1 / ORX1 Transmit Register Upper Word
Receive Register Upper Word
X:$FF FFFE OTX / ORX (32 bits) Transmit Register
Receive Register
X:$FF FFFD OTXRXSR Transmit and Receive Status and Control Register
X:$FF FFFC OCLSR Core Lock / Unlock Status Register
X:$FF FFFB - X:$FF FFA1 Reserved
X:$FF FFA0 OCR Control Register
X:$FF FF9F Instruction Step Counter
X:$FF FF9E OSCNTR (24 bits) Instruction Step Counter
X:$FF FF9D OSR Status Register
X:$FF FF9C OBASE Peripheral Base Address Register
X:$FF FF9B OTBCR Trace Buffer Control Register
X:$FF FF9A OTBPR Trace Buffer Pointer Register
X:$FF FF99 Trace Buffer Register Stages
X:$FF FF98 OTB (21 - 24 bits/stage) Trace Buffer Register Stages
X:$FF FF97 Breakpoint Unit Control Register
X:$FF FF96 OBCR (24 bits) Breakpoint Unit Control Register
X:$FF FF95 Breakpoint Unit Address Register 1
X:$FF FF94 OBAR1 (24 bits) Breakpoint Unit Address Register 1
X:$FF FF93 Breakpoint Unit Address Register 2
Reserved
RAM
Flash
Reserved
EOnCE
Peripherals
Reserved
RAM
Dual Port RAM
Program
Data
Reserved