Datasheet

Program Map
56F8037/56F8027 Data Sheet, Rev. 8
Freescale Semiconductor 47
4.3 Program Map
The Program Memory map is shown in Table 4-3 and Table 4-4.
CMPA 53 0-2 P:$6A Comparator A
CMPB 54 0-2 P:$6C Comparator B
PIT0 55 0-2 P:$6E Interval Timer 0
PIT1 56 0-2 P:$70 Interval Timer 1
PIT2 57 0-2 P:$72 Interval Timer 2
ADC 58 0-2 P:$74 ADC A Conversion Complete
ADC 59 0-2 P:$76 ADC B Conversion Complete
ADC 60 0-2 P:$78 ADC Zero Crossing or Limit Error
PWM 61 0-2 P:$7A Reload PWM
PWM 62 0-2 P:$7C PWM Fault
SWILP 63 -1 P:$7E SW Interrupt Low Priority
1. Two words are allocated for each entry in the vector table. This does not allow the full address range to be referenced
from the vector table, providing only 19 bits of address.
2. If the VBA is set to the reset value, the first two locations of the vector table will overlay the chip reset addresses since
the reset address would match the base of this vector table.
Table 4-3 Program Memory Map
1
at Reset for 56F8037
1. All addresses are 16-bit Word addresses.
Begin/End Address Memory Allocation
P: $1F FFFF
P: $00 9000
RESERVED
P: $00 8FFF
P: $00 8000
On-Chip RAM
2
8KB
2. This RAM is shared with Data space starting at address X: $00 0000; see Figure 4-1.
P: $00 7FFF
P: $00 0000
Internal Program Flash
64KB
Cop Reset Address = $00 0002
Boot Location = $00 0000
Table 4-2 Interrupt Vector Table Contents
1
(Continued)
Peripheral
Vector
Number
Priority
Level
Vector Base
Address +
Interrupt Function