Datasheet

56F8037/56F8027 Data Sheet, Rev. 8
32 Freescale Semiconductor
GPIOB4
(SS1
)
(TB0
18
)
(TA0
19
)
(PSRC2)
(CLKO)
38 Input/
Output
Input/
Output
Input/
Output
Input/
Output
Input
Output
Input,
internal
pull-up
enabled
Port B GPIO — This GPIO pin can be individually programmed as
an input or output pin.
QSPI1 Slave Select — This is used in slave mode to indicate to the
QSPI1 module that the current transfer is to be received.
TB0 — Timer B, Channel 0
TA0 — Timer A, Channel 0
PSRC2 — External PWM signal source input for the complementary
PWM0/PWM1 pair.
Clock Output — This is a buffered clock output; the clock source is
selected by Clockout Select (CLKOSEL) bits in the Clock Output
Select Register (CLKOUT). See Section 6.3.7.
After reset, the default state is GPIOB4. The peripheral functionality
is controlled via the SIM. See Section 6.3.16.
18
The TB0 signal is also brought out on the GPIOB4 and GPIOB10 pins.
19
The TA0 signal is also brought out on the GPIOB4 and GPIOA6 pins.
GPIOB5
(TA1
20
)
(FAULT3)
(CLKIN)
4 Input/
Output
Input/
Output
Input
Input
Input,
internal
pull-up
enabled
Port B GPIO — This GPIO pin can be individually programmed as
an input or output pin.
TA1 — Timer A, Channel 1
FAULT3 — This fault input pin is used for disabling selected PWM
outputs in cases where fault conditions originate off-chip.
External Clock Input— This pin serves as an external clock input.
After reset, the default state is GPIOB5. The peripheral functionality
is controlled via the SIM. See Section 6.3.16.
20
The TA1 signal is also brought out on the GPIOA12 pin.
Return to Table 2-2
Table 2-3 56F8037/56F8027 Signal and Package Information for the 64-Pin LQFP (Continued)
Signal
Name
LQFP
Pin No.
Type
State During
Reset
Signal Description