Datasheet

56F8037/56F8027 Data Sheet, Rev. 8
30 Freescale Semiconductor
GPIOB0
(SCLK0)
(SCL
14
)
42 Input/
Output
Input/
Output
Input/
Output
Input,
internal
pull-up
enabled
Port B GPIO — This GPIO pin can be individually programmed as
an input or output pin.
QSPI0 Serial Clock — In the master mode, this pin serves as an
output, clocking slaved listeners. In slave mode, this pin serves as
the data clock input. A Schmitt trigger input is used for noise
immunity.
Serial Clock — This pin serves as the I
2
C serial clock.
After reset, the default state is GPIOB0. The peripheral functionality
is controlled via the SIM. See Section 6.3.16.
14
The SCL signal is also brought out on the GPIOB7 and GPIOB8 pins.
GPIOB1
(SS
0)
(SDA
15
)
2 Input/
Output
Input/
Output
Input
Input,
internal
pull-up
enabled
Port B GPIO — This GPIO pin can be individually programmed as
an input or output pin.
QSPI0 Slave Select — SS
is used in slave mode to indicate to the
QSPI0 module that the current transfer is to be received.
Serial Data — This pin serves as the I
2
C serial data line.
After reset, the default state is GPIOB1. The peripheral functionality
is controlled via the SIM. See Section 6.3.16.
15
The SDA signal is also brought out on the GPIOB6 and GPIOB9 pins.
Return to Table 2-2
Table 2-3 56F8037/56F8027 Signal and Package Information for the 64-Pin LQFP (Continued)
Signal
Name
LQFP
Pin No.
Type
State During
Reset
Signal Description