Datasheet

56F8037/56F8027 Data Sheet, Rev. 8
2 Freescale Semiconductor
Document Revision History
Version History Description of Change
Rev. 0
Initial public release.
Rev. 1 • In Table 10-4, added an entry for flash data retention with less than 100 program/erase
cycles (minimum 20 years).
• In Table 10-6, changed the device clock speed in STOP mode from 8MHz to 4MHz.
• In Table 10-12, changed the typical relaxation oscillator output frequency in Standby mode
from 400kHz to 200kHz.
• Changed input propagation delay values in Table 10-21 as follows:
Old values: 1 s typical, 2 s maximum
New values: 35 ns typical, 45 ns maximum
Rev. 2
In Table 10-20, changed the maximum ADC internal clock frequency from 8MHz to 5.33MHz.
Rev. 3 • Added the following note to the description of the TMS signal in Table 2-3:
Note: Always tie the TMS pin to V
DD
through a 2.2K resistor.
• Changed the description of the GPIOC4 signal in Table 2-3 (was “...the signal goes to both
the ANA0 and CMPAI3”, is “...the signal goes to both ANB0 and CMPB13”).
Rev. 4 • Changed the ITCN_BASE address In Table 5-3 (was $00 F060, is $00 F0E0).
•In Figure 5-10, moved the footnote marker (superscript 1) from bit 4 to “RESET”.
• Changed the STANDBY > STOP I
DD
values in Table 10-6 as follows:
Typical: was 290A, is 540A
Maximum: was 390A, is 650A
• Changed the POWERDOWN I
DD
values in Table 10-6 as follows:
Typical: was 190A, is 440A
Maximum: was 250A, is 550A
• Changed footnote 1 in Table 10-12 (was “Output frequency after application of 8MHz trim
value, at 125°C.”, is “Output frequency after application of factory trim”).
• Deleted the text “at 125°C” from Figure 10-5.
• Changed the maximum input offset voltage in Table 10-21 (was +/- 20 mV, is ±35 mV).
Rev. 5 • In Table 2-3, changed V
CAP
value from 4.7F to 2.2F.
• Revised Section 7, Security Features.
• Added information for 56F8027 device throughout document.
• Fixed miscellaneous typos.