Datasheet

Architecture Block Diagram
56F8037/56F8027 Data Sheet, Rev. 8
Freescale Semiconductor 17
Figure 1-7 56F8037/56F8027 I/O Pin-Out Muxing (Part 5/5)
To/From IPBus Bridge
IPBus
TMRA
T0o
T0i
T1o
T1i
T2o
T2i
T3o
T3i
TA0o on Figure 1-6 (PWM)
TA0 on Figure 1-6 (GPIOA6)
TA0 on Figure 1-4 (GPIOB4)
TA1 on Figure 1-4(GPIOA12)
TA1 on Figure 1-6 (GPIOB5)
CMPAO on Figure 1-6 (CMPA)
SYNC1 on Figure 1-3 (ADC)
TA2o on Figure 1-6 (PWM)
TA2 on Figure 1-6 (GPIOA4)
TA2 on Figure 1-5 (GPIOA8)
TA2 on Figure 1-4 (GPIOA13)
TA2 on Figure 1-4 (GPIOB2)
CMPBO on Figure 1-6 (CMPB)
SYNC0 on Figure 1-3 (ADC)
TA3o on Figure 1-6 (PWM)
TA3 on Figure 1-6 (GPIOA5)
TA3 on Figure 1-5 (GPIOA9)
TA3 on Figure 1-4 (GPIOA14)
TA 3 on Figure 1-4 (GPIOB3)
RELOAD on Figure 1-6 (PWM)