Datasheet

56F8037/56F8027 Data Sheet, Rev. 8
160 Freescale Semiconductor
Figure 10-15 Timing Definition for Fast and Standard Mode Devices on the I
2
C Bus
Set-up time for STOP
condition
t
SU; STO
4.0 — 0.6 — s
Bus free time between
STOP and START
condition
t
BUF
4.7 — 1.3 — s
Pulse width of spikes that
must be suppressed by
the input filter
t
SP
N/A N/A 0 50 ns
1. The master mode I
2
C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
acknowledge this address byte, a negative hold time can result, depending on the edge rates of the SDA and SCL lines.
2. The maximum t
HD; DAT
must be met only if the device does not stretch the LOW period (t
LOW
) of the SCL signal.
3. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
4. A Fast mode I
2
C bus device can be used in a Standard mode I
2
C bus system, but the requirement t
SU; DAT
>= 250ns
must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal.
If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
t
rmax
+ t
SU; DAT
= 1000 + 250 = 1250ns (according to the Standard mode I
2
C bus specification) before the SCL line is
released.
5. C
b
= total capacitance of the one bus line in pF
Table 10-18 I
2
C Timing (Continued)
Characteristic Symbol
Standard Mode Fast Mode
Unit
Minimum Maximum Minimum Maximum
SDA
SCL
t
HD; STA
t
HD; DAT
t
LOW
t
SU; DAT
t
HIGH
t
SU; STA
SR
P
S
S
t
HD; STA
t
SP
t
SU; STO
t
BUF
t
f
t
r
t
f
t
r