Datasheet

Freescale’s Scalable Controller Area Network (MSCAN) Timing
56F8037/56F8027 Data Sheet, Rev. 8
Freescale Semiconductor 159
10.12 Freescale’s Scalable Controller Area Network (MSCAN)
Timing
Figure 10-14 Bus Wake-up Detection
10.13 Inter-Integrated Circuit Interface (I
2
C) Timing
Table 10-17 MSCAN Timing
1
1. Parameters listed are guaranteed by design
Characteristic Symbol Min Max Unit
Baud rate BR
CAN
— 1 Mbps
Bus wake-up detection T
WAKEUP
T
IPBUS
—µs
Table 10-18 I
2
C Timing
Characteristic Symbol
Standard Mode Fast Mode
Unit
Minimum Maximum Minimum Maximum
SCL Clock Frequency f
SCL
01000400kHz
Hold time (repeated)
START condition. After
this period, the first clock
pulse is generated.
t
HD; STA
4.0 — 0.6 — s
LOW period of the SCL
clock
t
LOW
4.7 — 1.3 — s
HIGH period of the SCL
clock
t
HIGH
4.0 — 0.6 — s
Set-up time for a repeated
START condition
t
SU; STA
4.7 — 0.6 — s
Data hold time for I
2
C bus
devices
t
HD; DAT
0
1
3.45
2
0
1
0.9
2
s
Data set-up time t
SU; DAT
250
3
—
100
3, 4
—ns
Rise time of both SDA and
SCL signals
t
r
— 1000
20 +0.1C
b
5
300 ns
Fall time of both SDA and
SCL signals
t
f
—300
20 +0.1C
b
5
300 ns
T
WAKEUP
MSCAN_RX
CAN receive
data pin
(Input)