Datasheet

Architecture Block Diagram
56F8037/56F8027 Data Sheet, Rev. 8
Freescale Semiconductor 13
Figure 1-3 56F8037/56F8027 I/O Pin-Out Muxing (Part 1/5)
To/From IPBus Bridge
IPBus
3
DAC SYNC on Figure 1-5
INTC
PIT0
PIT1
PIT2
SYNC
SYNC
SYNC
MSTR_CNT_EN
MSTR_CNT_EN
MSTR_CNT_EN
Sync0,
Sync1
3
2
SYNC0, SYNC1 on Figure 1-7
LIMIT on Figure 1-6
Over/Under
Limits
ANA1, 5-7
ANB1, 5-7
ANA4
ANB4
ADC
GPIOC1, 9-11
GPIOC5, 13-15
ANA0
ANA0 on Figure 1-5
ANA2 (V
REFHA
)
GPIOC2
ANA3 (V
REFLA
)
GPIOC3
ANB0
ANB0 on Figure 1-5
ANB3 (V
REFLB
)
GPIOC7
ANB2 (V
REFHA
)
GPIOC6
ANA4 on Figure 1-4
ANA1, 5-7
4
ANB4 on Figure 1-4
ANB1, 5-7
4