Datasheet

56F8037/56F8027 Data Sheet, Rev. 8
120 Freescale Semiconductor
Figure 6-24 Overall Control of Signal Source using SIM_IPSn Control
IPSn settings should not be altered while an affected peripheral is in an enabled (operational)
configuration. See the 56F802x and 56F803x Peripheral Reference Manual for details.
Figure 6-25 Internal Peripheral Source Select Register for PWM (SIM_IPS0)
6.3.21.1 Reserved—Bits 15–14
This bit field is reserved. Each bit must be set to 0.
6.3.21.2 Select Peripheral Input Source for FAULT2 (IPS0_FAULT2)—Bit 13
This field selects the alternate input source signal to feed PWM input FAULT2.
• 0 = I/O Pin (External) - Use PWM FAULT2 Input Pin (default)
• 1 = CMPBO (Internal) - Use Comparator B Output
6.3.21.3 Reserved—Bit 12
This bit field is reserved. It must be set to 0.
6.3.21.4 Select Peripheral Input Source for FAULT1 (IPS0_FAULT1)—Bit 11
This field selects the alternate input source signal to feed PWM input FAULT1.
• 0 = I/O pin (External) - Use PWM FAULT2 Input Pin (default)
• 1 = CMPAO (Internal) - Use Comparator A Output
Base + $18 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
0 0
IPS0_
FAULT2
0
IPS0_
FAULT1
0 0
IPS0_PSRC2 IPS0_PSRC1 IPS0_PSRC0
Write
RESET
00 0 0 0 00000000000
GPIOA5_PEREN
Register
GPIOA5
GPIOA5 pin
SIM_IPS0
Register
PWM
FAULT2
Comparator A
Output (Internal)
0
1
0
1
01
00
10
PWM5
Timer A3
SIM_GPSA0
Register