Datasheet

56F8037/56F8027 Data Sheet, Rev. 8

Freescale Semiconductor 105

6.3.10.1 Reserved—Bit 15

This bit field is reserved. It must be set to 0.

6.3.10.2 Programmable Interval Timer 2 Clock Enable (PIT2)—Bit 14

• 0 = The clock is not provided to the PIT2 module (the PIT2 module is disabled)

• 1 = The clock is enabled to the PIT2 module

6.3.10.3 Programmable Interval Timer 1 Clock Enable (PIT1)—Bit 13

• 0 = The clock is not provided to the PIT1 module (the PIT1 module is disabled)

• 1 = The clock is enabled to the PIT1 module

6.3.10.4 Programmable Interval Timer 0 Clock Enable (PIT0)—Bit 12

• 0 = The clock is not provided to the PIT0 module (the PIT0 module is disabled)

• 1 = The clock is enabled to the PIT0 module

6.3.10.5 Reserved—Bits 11–8

This bit field is reserved. Each bit must be set to 0.

6.3.10.6 Quad Timer B, Channel 3 Clock Enable (TB3)—Bit 7

• 0 = The clock is not provided to the Timer B3 module (the Timer B3 module is disabled)

• 1 = The clock is enabled to the Timer B3 module

6.3.10.7 Quad Timer B, Channel 2 Clock Enable (TB2)—Bit 6

• 0 = The clock is not provided to the Timer B2 module (the Timer B2 module is disabled)

• 1 = The clock is enabled to the Timer B2 module

6.3.10.8 Quad Timer B, Channel 1 Clock Enable (TB1)—Bit 5

• 0 = The clock is not provided to the Timer B1 module (the Timer B1 module is disabled)

• 1 = The clock is enabled to the Timer B1 module

6.3.10.9 Quad Timer B, Channel 0 Clock Enable (TB0)—Bit 4

• 0 = The clock is not provided to the Timer B0 module (the Timer B0 module is disabled)

• 1 = The clock is enabled to the Timer B0 module

6.3.10.10 Quad Timer A, Channel 3 Clock Enable (TA3)—Bit 3

• 0 = The clock is not provided to the Timer A3 module (the Timer A3 module is disabled)

• 1 = The clock is enabled to the Timer A3 module

6.3.10.11 Quad Timer A, Channel 2 Clock Enable (TA2)—Bit 2

• 0 = The clock is not provided to the Timer A2 module (the Timer A2 module is disabled)

• 1 = The clock is enabled to the Timer A2 module