Datasheet

56F8037/56F8027 Data Sheet, Rev. 8
104 Freescale Semiconductor
6.3.9.7 Reserved—Bits 9–7
This bit field is reserved. Each bit must be set to 0.
6.3.9.8 Inter-Integrated Circuit IPBus Clock Enable (I2C)—Bit 6
• 0 = The clock is not provided to the I
2
C module (the I
2
C module is disabled)
• 1 = The clock is enabled to the I
2
C module
6.3.9.9 QSCI 1 Clock Enable (QSCI1)—Bit 5
• 0 = The clock is not provided to the QSCI1 module (the QSCI1 module is disabled)
• 1 = The clock is enabled to the QSCI1 module
6.3.9.10 QSCI 0 Clock Enable (QSCI0)—Bit 4
• 0 = The clock is not provided to the QSCI0 module (the QSCI0 module is disabled)
• 1 = The clock is enabled to the QSCI0 module
6.3.9.11 QSPI 1 Clock Enable (QSPI1)—Bit 3
• 0 = The clock is not provided to the QSPI1 module (the QSPI1 module is disabled)
• 1 = The clock is enabled to the QSPI1 module
6.3.9.12 QSPI 0 Clock Enable (QSPI0)—Bit 2
• 0 = The clock is not provided to the QSPI0 module (the QSPI0 module is disabled)
• 1 = The clock is enabled to the QSPI0 module
6.3.9.13 Reserved—Bit 1
This bit field is reserved. It must be set to 0.
6.3.9.14 PWM Clock Enable (PWM)—Bit 0
• 0 = The clock is not provided to the PWM module (the PWM module is disabled)
• 1 = The clock is enabled to the PWM module
6.3.10 Peripheral Clock Enable Register 1 (SIM_PCE1)
See Section 6.3.9 for general information about Peripheral Clock Enable registers.
Figure 6-11 Peripheral Clock Enable Register 1 (SIM_PCE1)
Base + $D 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
0
PIT2 PIT1 PIT0
0 0 0 0
TB3 TB2 TB1 TB0 TA3 TA2 TA1 TA0
Write
RESET
0000000 0 00000 0 0 0