56F8037/56F8027 Data Sheet Technical Data 56F8000 16-bit Digital Signal Controllers MC56F8037 Rev. 8 04/2012 freescale.
Document Revision History Version History Description of Change Rev. 0 Initial public release. Rev. 1 • In Table 10-4, added an entry for flash data retention with less than 100 program/erase cycles (minimum 20 years). • In Table 10-6, changed the device clock speed in STOP mode from 8MHz to 4MHz. • In Table 10-12, changed the typical relaxation oscillator output frequency in Standby mode from 400kHz to 200kHz.
Document Revision History Version History Description of Change Rev.
56F8037/56F8027 General Description • Up to 32 MIPS at 32MHz core frequency • Three Programmable Interval Timers (PITs) • DSP and MCU functionality in a unified, C-efficient architecture • Two Queued Serial Communication Interfaces (QSCIs) with LIN slave functionality • 56F8037 offers 64KB (32K x 16) Program Flash • Two Queued Serial Peripheral Interfaces (QSPIs) • 56F8027 offers 32KB (16K x 16) Program Flash • Freescale’s scalable controller area network (MSCAN) 2.
6F8037/56F8027 Data Sheet Table of Contents Part 1 Overview. . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 1.2 1.3 1.4 1.5 1.6 56F8037/56F8027 Features . . . . . . . . . . . 6 56F8037/56F8027 Description . . . . . . . . . 8 Award-Winning Development Environment . . . . . . . . . . . . . . . . . . . 9 Architecture Block Diagram . . . . . . . . . . . 9 Product Documentation . . . . . . . . . . . . . 18 Data Sheet Conventions . . . . . . . . . . . . . 18 Part 2 Signal/Connection Descriptions . . .
Part 1 Overview 1.1 56F8037/56F8027 Features 1.1.1 • • • • • • • • • • • • • • 1.1.
56F8037/56F8027 Features 1.1.
— Full-duplex operation — Master and slave modes — Four-words-deep FIFOs available on both transmitter and receiver — Programmable Length Transactions (2 to 16 bits) • One Inter-Integrated Circuit (I2C) port — Operates up to 400kbps — Supports both master and slave operation — Supports both 10-bit address mode and broadcasting mode • One Freescale scalable controller area network (MSCAN) module — Fully compliant with CAN protocol - Version 2.
Award-Winning Development Environment configuration flexibility, and compact program code, the 56F8037/56F8027 is well-suited for many applications. The 56F8037/56F8027 includes many peripherals that are especially useful for industrial control, motion control, home appliances, general purpose inverters, smart sensors, fire and security systems, switched-mode power supply, power management, and medical monitoring applications.
connections to the PWM from the TMR and GPIO. These signals can control the PWM outputs in a similar manner as the PWM generator. See the 56F802x and 56F803x Peripheral Reference Manual for additional information. The PWM_reload_sync output can be connected to Timer A’s (TMRA) Channel 3 input; TMRA’s Channels 2 and 3 outputs are connected to the ADC sync inputs. TMRA Channel 3 output is connected to SYNC0 and TMRA Channel 2 is connected to SYNC1.
Architecture Block Diagram DSP56800E Core Program Control Unit PC LA LA2 HWS0 HWS1 FIRA OMR SR LC LC2 FISR Address Generation Unit (AGU) Instruction Decoder Interrupt Unit ALU1 ALU2 R0 R1 R2 R3 R4 R5 N M01 N3 Looping Unit Program Memory SP XAB1 XAB2 PAB PDB Data / Program RAM CDBW CDBR XDB2 A2 B2 C2 D2 BitManipulation Unit Enhanced OnCE™ JTAG TAP Y A1 B1 C1 D1 Y1 Y0 X0 MAC and ALU A0 B0 C0 D0 IPBUS Interface Data Arithmetic Logic Unit (ALU) Multi-Bit Shifter Figure 1-1 56800E Core Bloc
To/From IPBus Bridge OCCS (ROSC / PLL / OSC) Interrupt Controller Low-Voltage Interrupt GPIO A POR & LVI GPIO B System POR GPIO C SIM GPIO D RESET (Muxed with GPIOA7) COP Reset COP IPBus (Continues on Figure 1-3) Figure 1-2 Peripheral Subsystem 56F8037/56F8027 Data Sheet, Rev.
Architecture Block Diagram To/From IPBus Bridge IPBus INTC SYNC PIT0 MSTR_CNT_EN 3 MSTR_CNT_EN DAC SYNC on Figure 1-5 SYNC PIT1 MSTR_CNT_EN SYNC PIT2 2 3 Sync0, Sync1 Over/Under Limits SYNC0, SYNC1 on Figure 1-7 LIMIT on Figure 1-6 ANA0 ANA0 on Figure 1-5 GPIOC2 ANA2 (VREFHA) GPIOC3 ANA3 (VREFLA) ANA4 ANA1, 5-7 ADC ANB0 ANA4 on Figure 1-4 ANA1, 5-7 4 GPIOC1, 9-11 ANB0 on Figure 1-5 GPIOC6 ANB2 (VREFHA) GPIOC7 ANB3 (VREFLB) ANB4 ANB1, 5-7 ANB4 on Figure 1-4 ANB1, 5-7 4 GPIOC5, 13
To/From IPBus Bridge CLKO TA0 on Figure 1-7 GPIOB4 SS1 QSPI1 3 TA1-3 on Figure 1-7 SCLK1, MISO1, MOSI1 3 GPIOA12 - 14 3 TB0 on Figure 1-5 T0 TMRB TB1 on Figure 1-5 T1 T2, T3 1 2 QSCI0 2 TB2, TB3 on Figure 1-5 2 GPIOB6 - 7 RXD0, TXD0 2 TA2, TA3 on Figure 1-7 MISO0, MOSI0 QSPI0 GPIOB2 - 3 2 SCLK0, SS0 2 2 I2C SCL, SDA GPIOB0 - 1 2 2 2 GPIOB8 - 9 2 MSCAN CANTX, CANRX 2 2 ANA4, ANB4 on Figure 1-3 QSCI1 TXD1, RXD1 GPIOB12 - 13 2 GPIOC8 - 12 2 IPBus Figure 1-4 56F8037/56F802
Architecture Block Diagram To/From IPBus Bridge FAULT1 on Figure 1-6 TA2 on Figure 1-7 CMP_IN1 CMP_IN3 CMPAI1 CMPAI3 GPIOC0 CMPA CMP_OUT CMP_IN2 Export Import GPIOA8 CMPAO on Figure 1-6, Figure 1-7 CMPAI2 GPIOA10 ANA0 on Figure 1-3 TB2 on Figure 1-4 GPIOB10 DAC0 TB0 on Figure 1-4 2 3 DAC0 GPIOD6 DAC1 GPIOD7 TA0o, TA1o on Figure 1-7 DAC SYNC on Figure 1-3 RELOAD on Figure 1-6 TB1 on Figure 1-4 DAC1 TB3 on Figure 1-4 Import Export CMP_IN2 CMP_OUT ANB0 on Figure 1-3 GPIOB11 GPIOA11 CMPBI2
To/From IPBus Bridge TA0 on Figure 1-7 GPIOA6 2 TA2 - 3 on Figure 1-7 GPIOA0 - 3 4 PWM0 - 3 FAULT0 2 PWMA4 - 5 1 GPIOA4 - 5 2 PWM FAULT1 FAULT1 on Figure 1-5 CMPAO on Figure 1-5 FAULT2 RELOAD PSRC0 - 2 1 FAULT3 FAULT2 on Figure 1-5 CMPBO on Figure 1-5 TA1 on Figure 1-7 RELOAD on Figure 1-7, Figure 1-5 IPBus GPIOB5 CMPBO on Figure 1-5 CMPAO on Figure 1-5 3 3 3 3 GPIOB2 - 4 on Figure 1-4 LIMIT on Figure 1-3 TA0o, TA2o, TA3o on Figure 1-3 Figure 1-6 56F8037/56F8027 I/O Pin-Out Muxing (
Architecture Block Diagram To/From IPBus Bridge TA0o on Figure 1-6 (PWM) T0o T0i TA0 on Figure 1-6 (GPIOA6) TA0 on Figure 1-4 (GPIOB4) T1o T1i TA1 on Figure 1-4(GPIOA12) TA1 on Figure 1-6 (GPIOB5) CMPAO on Figure 1-6 (CMPA) SYNC1 on Figure 1-3 (ADC) TMRA TA2o on Figure 1-6 (PWM) TA2 on Figure 1-6 (GPIOA4) T2o T2i TA2 on Figure 1-5 (GPIOA8) TA2 on Figure 1-4 (GPIOA13) TA2 on Figure 1-4 (GPIOB2) CMPBO on Figure 1-6 (CMPB) SYNC0 on Figure 1-3 (ADC) TA3o on Figure 1-6 (PWM) TA3 on Figure 1-6 (GPIOA5)
1.5 Product Documentation The documents listed in Table 1-2 are required for a complete description and proper design with the 56F8037/56F8027. Documentation is available from local Freescale distributors, Freescale Semiconductor sales offices, Freescale Literature Distribution Centers, or online at: http://www.freescale.
Introduction Part 2 Signal/Connection Descriptions 2.1 Introduction The input and output signals of the 56F8037/56F8027 are organized into functional groups, as detailed in Table 2-1. Table 2-2 summarizes all device pins. In Table 2-2, each table row describes the signal or signals present on a pin, sorted by pin number.
In Table 2-2, peripheral pins in bold identify reset state.
Introduction Table 2-2 56F8037/56F8027 Pins (Continued) Peripherals: Pin # Pin Name 28 VCAP Signal Name GPIO I2C QSCI QSPI ADC PWM Quad Timer DAC Comp MSCAN VCAP Power & Ground JTAG Misc.
Table 2-2 56F8037/56F8027 Pins (Continued) Peripherals: Pin # Pin Name Signal Name GPIO I2C QSCI QSPI ADC PWM Quad Timer DAC Comp MSCAN Power & Ground JTAG 56 GPIOA0 GPIOA0, PWM0 A0 57 GPIOB12 GPIOB12, CANTX B12 CANTX 58 GPIOB13 GPIOB13, CANRX B13 CANRX 59 TDI TDI, GPIOD0 D0 60 GPIOB11 GPIOB11, CMPBO, TB1 B11 61 GPIOC15 GPIOC15, ANB7 C15 ANB7 62 GPIOC14 GPIOC14, ANB6 C14 ANB6 63 TMS TMS, GPIOD3 D3 TMS 64 TDO TDO, GPIOD1 D1 TDO Misc.
Introduction VDD Power VSS Ground VDDA Power VSSA Ground Other Supply Ports VCAP GPIOD4 (EXTAL) OSC Port or GPIO GPIOD5 (XTAL, CLKIN) 3 4 1 1 4 1 1 1 56F8037/56F8027 2 1 1 1 1 1 1 1 RESET or GPIOA RESET (GPIOA7) 1 1 1 GPIOB0 (SCLK0, SCL) QSPI0 or I2C or PWM or TMRA or GPIOB GPIOB1 (SS0, SDA) GPIOB2 (MISO0, TA2, PSRC0) GPIOB3 (MOSI0, TA3, PSRC1) 1 1 1 1 1 1 1 1 1 QSCI0 or PWM or I2C or TMRA or TMRB or QSPI1 or GPIOB GPIOB4 (SS1, TB0, TA0, PSRC2, CLKO) GPIOB5 (TA1, FAULT3, CLK
2.2 56F8037/56F8027 Signal Pins After reset, each pin is configured for its primary function (listed first). Any alternate functionality must be programmed. Table 2-3 56F8037/56F8027 Signal and Package Information for the 64-Pin LQFP Signal Name LQFP Pin No. Type State During Reset Signal Description VDD 7 Supply Supply I/O Power — This pin supplies 3.3V power to the chip I/O interface. VDD 41 VDD 50 VSS 8 Supply Supply VSS — These pins provide ground for chip logic and I/O drivers.
56F8037/56F8027 Signal Pins Table 2-3 56F8037/56F8027 Signal and Package Information for the 64-Pin LQFP (Continued) Signal Name LQFP Pin No. GPIOA0 56 (PWM0) Type Input/ Output State During Reset Input, internal pull-up enabled Output Signal Description Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. PWM0 — This is one of the six PWM output pins. After reset, the default state is GPIOA0.
Table 2-3 56F8037/56F8027 Signal and Package Information for the 64-Pin LQFP (Continued) Signal Name LQFP Pin No. GPIOA4 43 Type Input/ Output State During Reset Input, internal pull-up enabled Signal Description Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. (PWM4) Output PWM4 — This is one of the six PWM output pins.
56F8037/56F8027 Signal Pins Table 2-3 56F8037/56F8027 Signal and Package Information for the 64-Pin LQFP (Continued) Signal Name LQFP Pin No. GPIOA6 34 Type Input/ Output State During Reset Input, internal pull-up enabled Input (FAULT0) Signal Description Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. Fault0 — This fault input pin is used for disabling selected PWM outputs in cases where fault conditions originate off-chip. TA0 — Timer A, Channel 0.
Table 2-3 56F8037/56F8027 Signal and Package Information for the 64-Pin LQFP (Continued) Signal Name LQFP Pin No. GPIOA10 35 Type Input/ Output (TB26) Input/ Output (CMPAI2) Input State During Reset Input, internal pull-up enabled Signal Description Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. TB2 — Timer B, Channel 2. Comparator A, Input 2 — This is an analog input to Comparator A. After reset, the default state is GPIOA10.
56F8037/56F8027 Signal Pins Table 2-3 56F8037/56F8027 Signal and Package Information for the 64-Pin LQFP (Continued) Signal Name LQFP Pin No. GPIOA13 44 Type Input/ Output State During Reset Input, internal pull-up enabled Signal Description Port A GPIO — This GPIO pin can be individually programmed as an input or output pin. (MISO1) Input/ Output QSPI1 Master In/Slave Out— This serial data pin is an input to a master device and an output from a slave device.
Table 2-3 56F8037/56F8027 Signal and Package Information for the 64-Pin LQFP (Continued) Signal Name LQFP Pin No. GPIOB0 42 Type Input/ Output State During Reset Input, internal pull-up enabled Signal Description Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. (SCLK0) Input/ Output QSPI0 Serial Clock — In the master mode, this pin serves as an output, clocking slaved listeners. In slave mode, this pin serves as the data clock input.
56F8037/56F8027 Signal Pins Table 2-3 56F8037/56F8027 Signal and Package Information for the 64-Pin LQFP (Continued) Signal Name LQFP Pin No. GPIOB2 33 Type Input/ Output State During Reset Input, internal pull-up enabled Signal Description Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. (MISO0) Input/ Output QSPI0 Master In/Slave Out — This serial data pin is an input to a master device and an output from a slave device.
Table 2-3 56F8037/56F8027 Signal and Package Information for the 64-Pin LQFP (Continued) Signal Name LQFP Pin No. GPIOB4 38 Type Input/ Output State During Reset Input, internal pull-up enabled Signal Description Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. (SS1) Input/ Output QSPI1 Slave Select — This is used in slave mode to indicate to the QSPI1 module that the current transfer is to be received.
56F8037/56F8027 Signal Pins Table 2-3 56F8037/56F8027 Signal and Package Information for the 64-Pin LQFP (Continued) Signal Name LQFP Pin No. GPIOB6 1 Type Input/ Output (RXD0) Input (SDA21) Input/ Output (CLKIN) Input State During Reset Input, internal pull-up enabled Signal Description Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. Receive Data 0 — QSCI0 receive data input. Serial Data — This pin serves as the I2C serial data line.
Table 2-3 56F8037/56F8027 Signal and Package Information for the 64-Pin LQFP (Continued) Signal Name LQFP Pin No. GPIOB9 46 Type Input/ Output (SDA25) Input/ Output (CANRX26) Input State During Reset Input, internal pull-up enabled Signal Description Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. Serial Data 1 — This pin serves as the I2C serial data line. CAN Receive Data — This is the MSCAN interface input. After reset, the default state is GPIOB9.
56F8037/56F8027 Signal Pins Table 2-3 56F8037/56F8027 Signal and Package Information for the 64-Pin LQFP (Continued) Signal Name LQFP Pin No. GPIOB12 57 Type Input/ Output State During Reset Input Open Drain Output (CANTX29) Signal Description Port B GPIO — This GPIO pin can be individually programmed as an input or output pin. CAN Transmit Data — This is the MSCAN interface output. After reset, the default state is GPIOB12. 29 The CANTX signal is also brought out on the GPIOB8 pin.
Table 2-3 56F8037/56F8027 Signal and Package Information for the 64-Pin LQFP (Continued) Signal Name LQFP Pin No. GPIOC3 19 Type Input/ Output State During Reset Input Signal Description Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. (ANA3) Analog Input ANA3 — Analog input to ADC A, Channel 3. (VREFLA) Analog Input VREFLA — Analog reference voltage low. (ADC A). After reset, the default state is GPIOC3.
56F8037/56F8027 Signal Pins Table 2-3 56F8037/56F8027 Signal and Package Information for the 64-Pin LQFP (Continued) Signal Name LQFP Pin No. GPIOC7 14 Type Input/ Output (ANB3) Analog Input (VREFLB) Input State During Reset Input Signal Description Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. ANB3 — Analog input to ADC B, Channel 3. VREFLB — Analog reference voltage low (ADC B). After reset, the default state is GPIOC7.
Table 2-3 56F8037/56F8027 Signal and Package Information for the 64-Pin LQFP (Continued) Signal Name LQFP Pin No. GPIOC12 9 Type Input/ Output State During Reset Input Signal Description Port C GPIO — This GPIO pin can be individually programmed as an input or output pin. (ANB4) Analog Input ANB4 — Analog input to ADC B, Channel 4. (RXD1) Input Receive Data 1 — SCI1 receive data input. After reset, the default state is GPIOC12.
56F8037/56F8027 Signal Pins Table 2-3 56F8037/56F8027 Signal and Package Information for the 64-Pin LQFP (Continued) Signal Name LQFP Pin No. GPIOD5 52 Type Input/ Output (XTAL) Analog Input/ Output (CLKIN) Input State During Reset Input Signal Description Port D GPIO — This GPIO pin can be individually programmed as an input or output pin. External Crystal Oscillator Output — This output connects the internal crystal oscillator output to an external crystal.
Table 2-3 56F8037/56F8027 Signal and Package Information for the 64-Pin LQFP (Continued) Signal Name LQFP Pin No. Type TCK 29 Input (GPIOD2) State During Reset Input, internal pull-up enabled Input/ Output Signal Description Test Clock Input — This input pin provides a gated clock to synchronize the test logic and shift serial data to the JTAG/EOnCE port. The pin is connected internally to a pull-up resistor. A Schmitt trigger input is used for noise immunity.
Features 3.
3.4 Internal Clock Source An internal relaxation oscillator can supply the reference frequency when an external frequency source or crystal is not used. It is optimized for accuracy and programmability while providing several power-saving configurations which accommodate different operating conditions. The internal relaxation oscillator has very little temperature and voltage variability. To optimize power, the architecture supports a standby state and a power-down state.
Ceramic Resonator Crystal Frequency = 4 - 8MHz (optimized for 8MHz) EXTAL XTAL Rz EXTAL XTAL Rz Sample External Crystal Parameters: Rz = 750 K Note: If the operating temperature range is limited to below 85oC (105oC junction), then Rz = 10 Meg CL1 CL2 Figure 3-1 External Crystal Oscillator Circuit 3.6 Ceramic Resonator The internal crystal oscillator circuit is also designed to interface with a ceramic resonator in the frequency range of 4-8MHz.
56F8037/56F8027 CLKMODE = 1 XTAL EXTAL External Clock GND or GPIO Figure 3-3 Connecting an External Clock Signal using XTAL 3.8 Alternate External Clock Input The recommended method of connecting an external clock is illustrated in Figure 3-3. The external clock source is connected to GPIO6/RXD (primary) or GPIOB5/TA1/FAULT3/XTAL/EXTAL (secondary). The user has the option of using GPIO6/RXD/CLKIN or GPIOB5/TA1/FAULT3/CLKIN as external clock input.
Interrupt Vector Table Table 4-1 Chip Memory Configurations On-Chip Memory 56F8037 56F8027 Use Restrictions Program Flash (PFLASH) 32k x 16 or 64KB 16k x 16 or 32KB Erase / Program via Flash interface unit and word writes to CDBW Unified RAM (RAM) 4k x 16 or 8KB 2k x 16 or 4KB Usable by both the Program and Data memory spaces 4.2 Interrupt Vector Table Table 4-2 provides the 56F8037/56F8027’s reset and interrupt priority structure, including on-chip peripherals.
Table 4-2 Interrupt Vector Table Contents1 (Continued) Peripheral Vector Number Priority Level Vector Base Address + Interrupt Function LVI 15 1-3 P:$1E Low-Voltage Detector (Power Sense) PLL 16 1-3 P:$20 Phase-Locked Loop FM 17 0-2 P:$22 FM Access Error Interrupt FM 18 0-2 P:$24 FM Command Complete FM 19 0-2 P:$26 FM Command, Data, and Address Buffers Empty MSCAN 20 0-2 P:$28 MSCAN Error MSCAN 21 0-2 P:$2a MSCAN Receive MSCAN 22 0-2 P:$2C MSCAN Transmit MSCAN 2
Program Map Table 4-2 Interrupt Vector Table Contents1 (Continued) Peripheral Vector Number Priority Level Vector Base Address + Interrupt Function CMPA 53 0-2 P:$6A Comparator A CMPB 54 0-2 P:$6C Comparator B PIT0 55 0-2 P:$6E Interval Timer 0 PIT1 56 0-2 P:$70 Interval Timer 1 PIT2 57 0-2 P:$72 Interval Timer 2 ADC 58 0-2 P:$74 ADC A Conversion Complete ADC 59 0-2 P:$76 ADC B Conversion Complete ADC 60 0-2 P:$78 ADC Zero Crossing or Limit Error PWM 61 0-2 P
Table 4-4 Program Memory Map1 at Reset for 56F8027 Begin/End Address Memory Allocation P: $1F FFFF P: $00 8800 RESERVED P: $00 87FF P: $00 8000 On-Chip RAM2 4KB P: $00 7FFF P: $00 4000 Internal Program Flash 32KB Cop Reset Address = $00 4002 Boot Location = $00 4000 P: $00 3FFF P: $00 0000 RESERVED 1. All addresses are 16-bit Word addresses. 2. This RAM is shared with Data space starting at address X: $00 0000; see Figure 4-2. 4.
Data Map Program Data EOnCE Reserved Reserved RAM Peripherals Dual Port RAM Reserved Flash RAM Figure 4-1 Dual Port RAM for 56F8037 Table 4-6 Data Memory Map for 56F80271 Begin/End Address Memory Allocation X:$FF FFFF X:$FF FF00 EOnCE 256 locations allocated X:$FF FEFF X:$01 0000 RESERVED X:$00 FFFF X:$00 F000 On-Chip Peripherals 4096 locations allocated X:$00 EFFF X:$00 9000 RESERVED X:$00 8FFF X:$00 8000 RESERVED X:$00 7FFF X:$00 0800 RESERVED X:$00 07FF X:$00 0000 On-Chip Data RAM 4K
Program Data EOnCE Reserved Reserved RAM Peripherals Flash Dual Port RAM Reserved Reserved RAM Figure 4-2 Dual Port RAM for 56F8027 4.5 EOnCE Memory Map Figure 4-7 lists all EOnCE registers necessary to access or control the EOnCE.
Peripheral Memory-Mapped Registers Table 4-7 EOnCE Memory Map (Continued) Address X:$FF FF92 Register Acronym OBAR2 (32 bits) Register Name Breakpoint Unit Address Register 2 X:$FF FF91 Breakpoint Unit Mask Register 2 X:$FF FF90 OBMSK (32 bits) Breakpoint Unit Mask Register 2 X:$FF FF8F Reserved X:$FF FF8E OBCNTR EOnCE Breakpoint Unit Counter X:$FF FF8D Reserved X:$FF FF8C Reserved X:$FF FF8B Reserved X:$FF FF8A OESCR External Signal Control Register X:$FF FF89 - X:$FF FF00 Reserved
Table 4-8 Data Memory Peripheral Base Address Map Summary (Continued) Peripheral Prefix Base Address Table Number DAC 0 DAC0 X:$00 F1C0 4-25 DAC 1 DAC1 X:$00 F1D0 4-26 Comparator A CMPA X:$00 F1E0 4-27 Comparator B CMPB X:$00 F1F0 4-28 QSCI 0 QSCI0 X:$00 F200 4-29 QSCI 1 QSCI1 X:$00 F210 4-30 QSPI 0 QSPI0 X:$00 F220 4-31 QSPI 1 QSPI1 X:$00 F230 4-32 I2C X:$00 F280 4-33 2 I C FM FM X:$00 F400 4-34 MSCAN CAN X:$00 F800 4-35 56F8037/56F8027 Data Sheet, Rev.
Peripheral Memory-Mapped Registers Table 4-9 Quad Timer A Registers Address Map (TMRA_BASE = $00 F000) Register Acronym Address Offset Register Description TMRA0_COMP1 $0 Compare Register 1 TMRA0_COMP2 $1 Compare Register 2 TMRA0_CAPT $2 Capture Register TMRA0_LOAD $3 Load Register TMRA0_HOLD $4 Hold Register TMRA0_CNTR $5 Counter Register TMRA0_CTRL $6 Control Register TMRA0_SCTRL $7 Status and Control Register TMRA0_CMPLD1 $8 Comparator Load Register 1 TMRA0_CMPLD2 $9 Comp
Table 4-9 Quad Timer A Registers Address Map (Continued) (TMRA_BASE = $00 F000) Register Acronym Address Offset Register Description TMRA2_CMPLD2 $29 Comparator Load Register 2 TMRA2_CSCTRL $2A Comparator Status and Control Register TMRA2_FILT $2B Input Filter Register Reserved TMRA3_COMP1 $30 Compare Register 1 TMRA3_COMP2 $31 Compare Register 2 TMRA3_CAPT $32 Capture Register TMRA3_LOAD $33 Load Register TMRA3_HOLD $34 Hold Register TMRA3_CNTR $35 Counter Register TMRA3_CTRL
Peripheral Memory-Mapped Registers Table 4-10 Quad Timer B Registers Address Map (Continued) (TMRB_BASE = $00 F040) Register Acronym Address Offset Register Description TMRB1_LOAD $13 Load Register TMRB1_HOLD $14 Hold Register TMRB1_CNTR $15 Counter Register TMRB1_CTRL $16 Control Register TMRB1_SCTRL $17 Status and Control Register TMRB1_CMPLD1 $18 Comparator Load Register 1 TMRB1_CMPLD2 $19 Comparator Load Register 2 TMRB1_CSCTRL $1A Comparator Status and Control Register TMRB1
Table 4-11 Analog-to-Digital Converter Registers Address Map (ADC_BASE = $00 F080) Register Acronym Address Offset Register Description ADC_CTRL1 $0 Control Register 1 ADC_CTRL2 $1 Control Register 2 ADC_ZXCTRL $2 Zero Crossing Control Register ADC_CLIST 1 $3 Channel List Register 1 ADC_CLIST 2 $4 Channel List Register 2 ADC_CLIST 3 $5 Channel List Register 3 ADC_CLIST 4 $6 Channel List Register 4 ADC_SDIS $7 Sample Disable Register ADC_STAT $8 Status Register ADC_RDY $9 Conv
Peripheral Memory-Mapped Registers Table 4-11 Analog-to-Digital Converter Registers Address Map (Continued) (ADC_BASE = $00 F080) Register Acronym Address Offset Register Description ADC_HILIM0 $24 High Limit Register 0 ADC_HILIM1 $25 High Limit Register 1 ADC_HILIM2 $26 High Limit Register 2 ADC_HILIM3 $27 High Limit Register 3 ADC_HILIM4 $28 High Limit Register 4 ADC_HILIM5 $29 High Limit Register 5 ADC_HILIM6 $2A High Limit Register 6 ADC_HILIM7 $2B High Limit Register 7 ADC_O
Table 4-12 Pulse Width Modulator Registers Address Map (Continued) (PWM_BASE = $00 F0C0) Register Acronym Address Offset Register Description PWM_DTIM1 $D Dead Time Register 1 PWM_DMAP1 $E Disable Mapping Register 1 PWM_DMAP2 $F Disable Mapping Register 2 PWM_CNFG $10 Configure Register PWM_CCTRL $11 Channel Control Register PWM_PORT $12 Port Register PWM_ICCTRL $13 Internal Correction Control Register PWM_SCTRL $14 Source Control Register PWM_SYNC $15 Synchronization Window Reg
Peripheral Memory-Mapped Registers Table 4-13 Interrupt Control Registers Address Map (Continued) (ITCN_BASE = $00 F0E0) Register Acronym ITCN_IRQP3 Address Offset $11 Register Description IRQ Pending Register 3 Reserved ITCN_ICTRL $16 Interrupt Control Register Reserved Table 4-14 SIM Registers Address Map (SIM_BASE = $00 F100) Register Acronym Address Offset Register Description SIM_CTRL $0 Control Register SIM_RSTAT $1 Reset Status Register SIM_SWC0 $2 Software Control Register 0 SIM_S
Table 4-15 Computer Operating Properly Registers Address Map (COP_BASE = $00 F120) Register Acronym Address Offset Register Description COP_CTRL $0 Control Register COP_TOUT $1 Time-Out Register COP_CNTR $2 Counter Register Table 4-16 Clock Generation Module Registers Address Map (OCCS_BASE = $00 F130) Register Acronym Address Offset Register Description OCCS_CTRL $0 Control Register OCCS_DIVBY $1 Divide-By Register OCCS_STAT $2 Status Register OCCS_OCTRL $5 Oscillator Control Regi
Peripheral Memory-Mapped Registers Table 4-18 GPIOA Registers Address Map (Continued) (GPIOA_BASE = $00 F150) Register Acronym GPIOA_IPEND Address Offset $7 Register Description Interrupt Pending Register GPIOA_IEDGE $8 Interrupt Edge-Sensitive Register GPIOA_PPOUTM $9 Push-Pull Output Mode Control Register GPIOA_RDATA $A Raw Data Input Register GPIOA_DRIVE $B Output Drive Strength Control Register Table 4-19 GPIOB Registers Address Map (GPIOB_BASE = $00 F160) Register Acronym Address Offse
Table 4-21 GPIOD Registers Address Map (GPIOD_BASE = $00 F180) Register Acronym Address Offset Register Description GPIOD_PUPEN $0 Pull-up Enable Register GPIOD_DATA $1 Data Register GPIOD_DDIR $2 Data Direction Register GPIOD_PEREN $3 Peripheral Enable Register GPIOD_IASSRT $4 Interrupt Assert Register GPIOD_IEN $5 Interrupt Enable Register GPIOD_IPOL $6 Interrupt Polarity Register GPIOD_IPEND $7 Interrupt Pending Register GPIOD_IEDGE $8 Interrupt Edge-Sensitive Register GPIOD
Peripheral Memory-Mapped Registers Table 4-24 Programmable Interval Timer 2 Registers Address Map (Continued) (PIT2_BASE = $00 F1B0) Register Acronym PIT2_CNTR Address Offset $2 Register Description Counter Register Table 4-25 Digital-to-Analog Converter 0 Registers Address Map (DAC0_BASE = $00 F1C0) Register Acronym Address Offset Register Description DAC0_CTRL $0 Control Register DAC0_DATA $1 Data Register DAC0_STEP $2 Step Register DAC0_MINVAL $3 Minimum Value Register DAC0_MAXVAL $4
Table 4-29 Queued Serial Communication Interface 0 Registers Address Map (QSCI0_BASE = $00 F200) Register Acronym Address Offset Register Description QSCI0_RATE $0 Baud Rate Register QSCI0_CTRL1 $1 Control Register 1 QSCI0_CTRL2 $2 Control Register 2 QSCI0_STAT $3 Status Register QSCI0_DATA $4 Data Register Table 4-30 Queued Serial Communication Interface 1 Registers Address Map (QSCI1_BASE = $00 F210) Register Acronym Address Offset Register Description QSCI1_RATE $0 Baud Rate Regist
Peripheral Memory-Mapped Registers Table 4-32 Queued Serial Peripheral Interface 1 Registers Address Map (QSPI1_BASE = $00 F230) Register Acronym QSPI1_DELAY Address Offset Register Description $5 Delay Register Table 4-33 I2C Registers Address Map (I2C_BASE = $00 F280) Register Acronym Address Offset Register Description I2C_CTRL $0 Control Register I2C_TAR $2 Target Address Register I2C_SAR $4 Slave Address Register I2C_DATA $8 RX/TX Data Buffer and Command Register I2C_SSHCNT $A St
Table 4-34 Flash Module Registers Address Map (FM_BASE = $00 F400) Register Acronym Address Offset Register Description FM_CLKDIV $0 Clock Divider Register FM_CNFG $1 Configuration Register $2 Reserved FM_SECHI $3 Security High Half Register FM_SECLO $4 Security Low Half Register $5 - $9 FM_PROT $10 Reserved Protection Register $11 - $12 Reserved FM_USTAT $13 User Status Register FM_CMD $14 Command Register $15 - $17 FM_DATA $18 Data Buffer Register $19 - $A FM_OPT1 FM_TSTSIG
Peripheral Memory-Mapped Registers Table 4-35 MSCAN Registers Address Map (Continued) (MSCAN_BASE = $00 F800) Register Acronym Address Offset Register Description MSCAN_IDAR0 $10 Identifier Acceptance Register 0 MSCAN_IDAR1 $11 Identifier Acceptance Register 1 MSCAN_IDAR2 $12 Identifier Acceptance Register 2 MSCAN_IDAR3 $13 Identifier Acceptance Register 3 MSCAN_IDMR0 $14 Identifier Mask Register 0 MSCAN_IDMR1 $15 Identifier Mask Register 1 MSCAN_IDMR2 $16 Identifier Mask Register 2
Table 4-35 MSCAN Registers Address Map (Continued) (MSCAN_BASE = $00 F800) Register Acronym Address Offset Register Description MSCAN_TXFG4 $34 Foreground Transmit Buffer 4 MSCAN_TXFG5 $35 Foreground Transmit Buffer 5 MSCAN_TXFG6 $36 Foreground Transmit Buffer 6 MSCAN_TXFG7 $37 Foreground Transmit Buffer 7 MSCAN_TXFG8 $38 Foreground Transmit Buffer 8 MSCAN_TXFG9 $39 Foreground Transmit Buffer 9 MSCAN_TXFG10 $3A Foreground Transmit Buffer 10 MSCAN_TXFG11 $3B Foreground Transmit Buff
Functional Description 5.3.1 Normal Interrupt Handling Once the INTC has determined that an interrupt is to be serviced and which interrupt has the highest priority, an interrupt vector address is generated. Normal interrupt handling concatenates the Vector Base Address (VBA) and the vector number to determine the vector address, generating an offset into the vector table for each interrupt. 5.3.
3. Setting the FIVALn and FIVAHn registers with the address of the code for the Fast Interrupt When an interrupt occurs, its vector number is compared with the FIM0 and FIM1 register values. If a match occurs, and it is a level 2 interrupt, the ITCN handles it as a Fast Interrupt. The ITCN takes the vector address from the appropriate FIVALn and FIVAHn registers, instead of generating an address that is an offset from the VBA.
Operating Modes 5.5 Operating Modes The ITCN module design contains two major modes of operation: • • Functional Mode The ITCN is in this mode by default. Wait and Stop Modes During Wait and Stop modes, the system clocks and the 56800E core are turned off. The ITCN will signal a pending IRQ to the System Integration Module (SIM) to restart the clocks and service the IRQ. An IRQ can only wake up the core if the IRQ is enabled prior to entering the Wait or Stop mode. 5.
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Register Descriptions 5.6.1 Interrupt Priority Register 0 (IPR0) Base + $0 Read 15 14 13 PLL IPL Write RESET 0 0 12 11 10 0 0 0 0 LVI IPL 0 0 9 8 RX_REG IPL 0 0 7 6 TX_REG IPL 0 0 5 4 TRBUF IPL 0 0 3 2 BKPT_U IPL 0 0 1 0 STPCNT IPL 0 0 Figure 5-3 Interrupt Priority Register 0 (IPR0) 5.6.1.
5.6.1.5 EOnCE Transmit Register Empty Interrupt Priority Level (TX_REG IPL)— Bits 7–6 This field is used to set the interrupt priority level for the EOnCE Transmit Register Empty IRQ. This IRQ is limited to priorities 1 through 3. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 1 10 = IRQ is priority level 2 11 = IRQ is priority level 3 5.6.1.
Register Descriptions 5.6.2 Interrupt Priority Register 1 (IPR1) Base + $1 Read 15 14 GPIOD IPL Write RESET 0 0 13 12 11 MSCAN_WK UP IPL 0 0 10 MSCAN_TX IPL 0 0 9 8 MSCAN_RX IPL 0 0 7 6 MSCAN_ERR IPL 0 0 5 4 FM_CBE IPL 0 0 3 2 FM_CC IPL 0 0 1 0 FM_ERR IPL 0 0 Figure 5-4 Interrupt Priority Register 1 (IPR1) 5.6.2.1 GPIOD Interrupt Priority Level (GPIOD IPL)—Bits 15–14 This field is used to set the interrupt priority level for the GPIOD IRQ.
• 11 = IRQ is priority level 2 5.6.2.5 MSCAN Error Interrupt Priority Level (MSCAN_ERR IPL)—Bits 7–6 This field is used to set the interrupt priority level for the MSCAN Error IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.2.
Register Descriptions 5.6.3 Interrupt Priority Register 2 (IPR2) Base + $2 Read 15 14 13 QSCI0_XMIT IPL Write RESET 0 0 12 11 QSPI1_XMIT IPL 0 0 10 QSPI1_RCV IPL 0 0 9 8 QSPI0_XMIT IPL 0 0 7 6 QSPI0_RCV IPL 0 0 5 4 GPIOA IPL 0 0 3 2 GPIOB IPL 0 0 1 0 GPIOC IPL 0 0 Figure 5-5 Interrupt Priority Register 2 (IPR2) 5.6.3.
• • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.3.5 QSPI 0 Receiver Full Interrupt Priority Level (QSPI0_RCV IPL)—Bits 7–6 This field is used to set the interrupt priority level for the QSPI0 Receiver Full IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.3.
Register Descriptions 5.6.4 Interrupt Priority Register 3 (IPR3) Base + $3 Read 15 14 I2C_ERR IPL Write RESET 0 0 13 12 QSCI1_RCV IPL 0 0 11 10 QSCI1_RER R IPL 0 0 9 8 QSCI1_TIDL IPL 0 0 7 6 QSCI1_XMIT IPL 0 0 5 4 QSCI0_RCV IPL 0 0 3 2 QSCI0_RERR IPL 0 0 1 0 QSCI0_TIDL IPL 0 0 Figure 5-6 Interrupt Priority Register 3 (IPR3) 5.6.4.1 I2C Error Interrupt Priority Level (I2C_ERR IPL)—Bits 15–14 This field is used to set the interrupt priority level for the I2C Error IRQ.
• 11 = IRQ is priority level 2 5.6.4.5 QSCI 1 Transmitter Empty Interrupt Priority Level (QSCI1_XMIT IPL)— Bits 7–6 This field is used to set the interrupt priority level for the QSCI1 Transmitter Empty IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.4.
Register Descriptions 5.6.5 Interrupt Priority Register 4 (IPR4) Base + $4 Read 15 14 TMRA_3 IPL Write RESET 0 0 13 12 TMRA_2 IPL 0 0 11 10 TMRA_1 IPL 0 0 9 8 TMRA_0 IPL 0 0 7 6 I2C_STAT IPL 0 0 5 4 I2C_TX IPL 0 0 3 2 I2C_RX IPL 0 0 1 0 I2C_GEN IPL 0 0 Figure 5-7 Interrupt Priority Register 4 (IPR4) 5.6.5.1 Timer A, Channel 3 Interrupt Priority Level (TMRA_3 IPL)— Bits 15–14 This field is used to set the interrupt priority level for the Timer A, Channel 3 IRQ.
5.6.5.4 Timer A, Channel 0 Interrupt Priority Level (TMRA_0 IPL)— Bits 9–8 This field is used to set the interrupt priority level for the Timer A, Channel 0 IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.5.5 I2C Status Interrupt Priority Level (I2C_STAT IPL)—Bits 7–6 This field is used to set the interrupt priority level for the I2C Status IRQ.
Register Descriptions • • 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.6 Interrupt Priority Register 5 (IPR5) Base + $5 Read Write RESET 15 14 13 12 PIT1 IPL PIT0 IPL 0 0 0 0 11 10 COMPB IPL 0 0 9 8 COMPA IPL 0 0 7 6 TMRB_3 IPL 0 0 5 4 TMRB_2 IPL 0 0 3 2 TMRB_1 IPL 0 0 1 0 TMRB_0 IPL 0 0 Figure 5-8 Interrupt Priority Register 5 (IPR6) 5.6.6.
5.6.6.4 Comparator A Interrupt Priority Level (COMPA IPL)— Bits 9–8 This field is used to set the interrupt priority level for the Comparator IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.6.5 Timer B, Channel 3 Interrupt Priority Level (TMRB_3 IPL)—Bits 7–6 This field is used to set the interrupt priority level for the Timer B, Channel 3 IRQ.
Register Descriptions • 11 = IRQ is priority level 2 5.6.7 Interrupt Priority Register 6 (IPR6) Base + $6 15 14 13 12 Read 0 0 0 0 0 0 0 0 Write RESET 11 10 PWM_F IPL 0 9 8 PWM_RL IPL 0 0 0 7 6 ADC_ZC IPL 0 0 5 4 ADCB_CC IPL 0 0 3 2 ADCA_CC IPL 0 0 1 0 PIT2 IPL 0 0 Figure 5-9 Interrupt Priority Register 6 (IPR6) 5.6.7.1 Reserved—Bits 15–12 This bit field is reserved. Each bit must be set to 0. 5.6.7.
5.6.7.5 ADC B Conversion Complete Interrupt Priority Level (ADCB_CC IPL)—Bits 5–4 This field is used to set the interrupt priority level for the ADC B Conversion Complete IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default. • • • • 00 = IRQ disabled (default) 01 = IRQ is priority level 0 10 = IRQ is priority level 1 11 = IRQ is priority level 2 5.6.7.
Register Descriptions 5.6.8.2 Vector Address Bus (VAB) Bits 13–0 The value in this register is used as the upper 14 bits of the interrupt vector VAB[20:0]. The lower 7 bits are determined based on the highest priority interrupt and are then appended onto VBA before presenting the full VAB to the Core. 5.6.
5.6.11 Fast Interrupt 0 Vector Address High Register (FIVAH0) Base + $A 15 14 13 12 11 10 9 8 7 6 5 Read 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 2 1 0 FAST INTERRUPT 0 VECTOR ADDRESS HIGH Write RESET 3 0 0 0 0 0 Figure 5-13 Fast Interrupt 0 Vector Address High Register (FIVAH0) 5.6.11.1 Reserved—Bits 15–5 This bit field is reserved. Each bit must be set to 0. 5.6.11.
Register Descriptions 5.6.13.1 Fast Interrupt 1 Vector Address Low (FIVAL1)—Bits 15–0 The lower 16 bits of the vector address used for Fast Interrupt 1. This register is combined with FIVAH1 to form the 21-bit vector address for Fast Interrupt 1 defined in the FIM1 register. 5.6.
5.6.16 IRQ Pending Register 1 (IRQP1) Base + $F 15 14 13 12 11 10 9 Read 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 PENDING[32:17] Write RESET 1 1 1 1 1 1 1 1 1 Figure 5-18 IRQ Pending Register 1 (IRQP1) 5.6.16.1 IRQ Pending (PENDING)—Bits 32–17 This register bit values represent the pending IRQs for interrupt vector numbers 17 through 32. Ascending IRQ numbers correspond to ascending bit locations.
Register Descriptions 5.6.18.2 Reserved—Bit 15 This bit field is reserved. When it is read, it has a value of 1. 5.6.19 Interrupt Control Register (ICTRL) $Base + $16 15 Read INT 14 13 12 11 10 IPIC 9 8 7 6 VAB Write RESET 0 0 0 0 0 0 0 0 0 0 5 4 3 2 1 0 INT_ DIS 1 1 1 0 0 0 1 1 1 0 0 Figure 5-21 Interrupt Control Register (ICTRL) 5.6.19.1 Interrupt (INT)—Bit 15 This read-only bit reflects the state of the interrupt to the 56800E core.
when the 56800E core jumps to a new interrupt service routine. Note: Nested interrupts may cause this field to be updated before the original interrupt service routine can read it. 5.6.19.4 Interrupt Disable (INT_DIS)—Bit 5 This bit allows all interrupts to be disabled. • • 0 = Normal operation (default) 1 = All interrupts disabled 5.6.19.5 Reserved—Bits 4-2 This bit field is reserved. Each bit must be set to 1. 5.6.19.6 Reserved—Bits 1–0 This bit field is reserved. Each bit must be set to 0. 5.
5.7.3 Introduction ITCN After Reset After reset, all of the ITCN registers are in their default states. This means all interrupts are disabled, except the core IRQs with fixed priorities: • • • • • • • • Illegal Instruction SW Interrupt 3 HW Stack Overflow Misaligned Long Word Access SW Interrupt 2 SW Interrupt 1 SW Interrupt 0 SW Interrupt LP These interrupts are enabled at their fixed priority levels. Part 6 System Integration Module (SIM) 6.
6.
Register Descriptions 6.3 Register Descriptions A write to an address without an associated register is an NOP. A read from an address without an associated register returns unknown data. Table 6-1 SIM Registers (SIM_BASE = $00 F100) Register Acronym Base Address + Register Name Section Location CTRL $0 Control Register 6.3.1 RSTAT $1 Reset Status Register 6.3.2 SWC0 $2 Software Control Register 0 6.3.3 SWC1 $3 Software Control Register 1 6.3.3 SWC2 $4 Software Control Register 2 6.
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Register Descriptions $1A SIM_IPS2 R 0 0 0 IPS2_ TA3 W 0 0 0 IPS2_ TA2 0 0 0 0 IPS2_ TA1 0 0 0 Reserved 0 = Read as 0 = Read as 1 1 = Reserved Figure 6-1 SIM Register Map Summary 6.3.1 SIM Control Register (SIM_CTRL) Base + $0 15 14 13 12 11 10 9 8 7 6 5 4 Read 0 0 0 0 0 0 0 0 0 0 ONCE EBL SW RST 0 0 0 0 0 0 0 0 0 0 0 0 Write RESET 3 2 1 0 STOP_ DISABLE WAIT_ DISABLE 0 0 0 0 Figure 6-2 SIM Control Register (SIM_CTRL) 6.3.1.
6.3.2 SIM Reset Status Register (SIM_RSTAT) This read-only register is updated upon any system reset and indicates the cause of the most recent reset. It indicates whether the COP reset vector or regular reset vector (including Power-On Reset, External Reset, Software Reset) in the vector table is used. This register is asynchronously reset during Power-On Reset and subsequently is synchronously updated based on the precedence level of reset inputs.
Register Descriptions 6.3.2.7 Reserved—Bits 1–0 This bit field is reserved. Each bit must be set to 0. 6.3.3 SIM Software Control Registers (SIM_SWC0, SIM_SWC1, SIM_SWC2, and SIM_SWC3) These registers are general-purpose registers. They are reset only at power-on, so they can monitor software execution flow.
6.3.6 SIM Power Control Register (SIM_PWR) This register controls the Standby mode of the large on-chip regulator. The large on-chip regulator derives the core digital logic power supply from the IO power supply. At a system bus frequency of 200kHz, the large regulator may be put in a reduced-power standby mode without interfering with device operation to reduce device power consumption.
Register Descriptions Base + $A 15 14 13 12 11 10 Read 0 0 0 0 0 0 0 0 0 0 0 0 Write RESET 9 8 PWM3 PWM2 0 0 7 6 PWM1 PWM0 0 0 5 4 3 CLK DIS 1 2 1 0 0 0 CLKOSEL 0 0 0 Figure 6-8 CLKO Select Register (SIM_CLKOUT) 6.3.7.1 Reserved—Bits 15–10 This bit field is reserved. Each bit must be set to 0. 6.3.7.
6.3.8 Peripheral Clock Rate Register (SIM_PCR) By default, all peripherals are clocked at the system clock rate, which has a maximum of 32MHz. Selected peripherals clocks have the option to be clocked at 3X system clock rate, which has a maximum of 96MHz, if the PLL output clock is selected as the system clock. If PLL is disabled, the 3X system clock will not be available. This register is used to enable high-speed clocking for those peripherals that support it.
Register Descriptions 6.3.9 Peripheral Clock Enable Register 0 (SIM_PCE0) The Peripheral Clock Enable register enables or disables clocks to the peripherals as a power savings feature. Significant power savings are achieved by enabling only the peripheral clocks that are in use. When a peripheral’s clock is disabled, that peripheral is in Stop mode. Accesses made to a module that has its clock disabled will have no effect.
6.3.9.7 Reserved—Bits 9–7 This bit field is reserved. Each bit must be set to 0. 6.3.9.8 Inter-Integrated Circuit IPBus Clock Enable (I2C)—Bit 6 • 0 = The clock is not provided to the I2C module (the I2C module is disabled) • 1 = The clock is enabled to the I2C module 6.3.9.9 • • QSCI 1 Clock Enable (QSCI1)—Bit 5 0 = The clock is not provided to the QSCI1 module (the QSCI1 module is disabled) 1 = The clock is enabled to the QSCI1 module 6.3.9.
Register Descriptions 6.3.10.1 Reserved—Bit 15 This bit field is reserved. It must be set to 0. 6.3.10.2 • • 0 = The clock is not provided to the PIT2 module (the PIT2 module is disabled) 1 = The clock is enabled to the PIT2 module 6.3.10.3 • • Programmable Interval Timer 1 Clock Enable (PIT1)—Bit 13 0 = The clock is not provided to the PIT1 module (the PIT1 module is disabled) 1 = The clock is enabled to the PIT1 module 6.3.10.
6.3.10.12 Quad Timer A, Channel 1 Clock Enable (TA1)—Bit 1 • • 0 = The clock is not provided to the Timer A1 module (the Timer A1 module is disabled) 1 = The clock is enabled to the Timer A1 module 6.3.10.13 Quad Timer A, Channel 0 Clock Enable (TA0)—Bit 0 • • 0 = The clock is not provided to the Timer A0 module (the Timer A0 module is disabled) 1 = The clock is enabled to the Timer A0 module 6.3.
Register Descriptions 6.3.11.3 • • 0 = The clock is disabled during Stop mode 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0 register 6.3.11.4 • • Digital-to-Analog Converter 1 Clock Stop Disable (DAC1_SD)—Bit 13 Digital-to-Analog Converter 0 Clock Stop Disable (DAC0_SD)—Bit 12 0 = The clock is disabled during Stop mode 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0 register 6.3.11.
• • 0 = The clock is disabled during Stop mode 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0 register 6.3.11.13 Reserved—Bit 1 This bit field is reserved. It must be set to 0. 6.3.11.14 PWM Clock Stop Disable (PWM_SD)—Bit 0 • • 0 = The clock is disabled during Stop mode 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0 register 6.3.12 Stop Disable Register 1 (SD1) See Section 6.3.
Register Descriptions 6.3.12.6 • • 0 = The clock is disabled during Stop mode 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1 register 6.3.12.7 • • Quad Timer B, Channel 1 Clock Stop Disable (TB1_SD)—Bit 5 0 = The clock is disabled during Stop mode 1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1 register 6.3.12.
of I/O address, which are “hard coded”. These registers allow access to peripherals using I/O short address mode, regardless of the physical location of the peripheral, as shown in Figure 6-14.
Register Descriptions Base + $11 15 14 13 12 11 10 9 8 Read 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 ISAL[21:6] Write RESET 1 1 1 1 1 1 1 1 1 Figure 6-16 I/O Short Address Location Low Register (SIM_IOSALO) 6.3.14.1 Input/Output Short Address Location (ISAL[21:6])—Bits 15–0 This field represents the lower 16 address bits of the “hard coded” I/O short address. 6.3.
• 11 = Write protection on and locked until chip reset 6.3.15.3 GPIO and Internal Peripheral Select Protection (GIPSP)—Bits 1–0 These bits enable write protection of GPSn and IPSn registers in the SIM module and write protect all GPIOx_PEREN, GPIOx_PPOUTM and GPIOx_DRIVE registers in GPIO modules.
Register Descriptions Note: After reset, all I/O pins are GPIO, except the JTAG pins and the RESET pin. Base + $13 15 14 13 Read 0 0 0 0 0 0 Write RESET 12 11 GPS_A6 0 10 9 8 GPS_A5 GPS_A4 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 6-19 GPIO Peripheral Select Register 0 for GPIOA (SIM_GPSA0) 6.3.16.1 Reserved—Bits 15–13 This bit field is reserved. Each bit must be set to 0. 6.3.16.
Base + $14 15 14 Read 0 0 0 0 Write RESET 13 12 11 10 9 8 GPS_A14 GPS_A13 GPS_A12 0 0 0 0 0 0 7 6 5 4 0 GPS_ A11 0 GPS_ A10 0 0 0 0 3 2 1 0 GPS_A9 GPS_A8 0 0 0 0 Figure 6-20 GPIO Peripheral Select Register 1 for GPIOA (SIM_GPSA1) 6.3.17.1 Reserved—Bits 15–14 This bit field is reserved. Each bit must be set to 0. 6.3.17.2 Configure GPIOA14 (GPS_A14)—Bits 13–12 This field selects the alternate function for GPIOA14.
Register Descriptions 6.3.17.7 Reserved—Bit 5 This bit field is reserved. It must be set to 0. 6.3.17.8 Configure GPIOA10 (GPS_A10)—Bit 4 This field selects the alternate function for GPIOA10. • • 0 = CMPAI2- Comparator A Input 2 (default) 1 = TB2 - Timer B2 6.3.17.9 Configure GPIOA9 (GPS_A9)—Bits 3–2 This field selects the alternate function for GPIOA9. • • • • 00 = FAULT2 - PWM FAULT2 Input (default) 01 = TA3 - Timer A3 10 = CMPBI1 - Comparator B Input 1 11 = Reserved 6.3.17.
• • 10 = CLKIN - External Clock Input 11 = Reserved 6.3.18.3 Configure GPIOB5 (GPS_B5)—Bits 12–11 This field selects the alternate function for GPIOB5. • • • • 00 = TA1 - Timer A1 (default) 01 = FAULT3 - PWM FAULT3 Input 10 = CLKIN - External Clock Input 11 = Reserved 6.3.18.4 Configure GPIOB4(GPS_B4)—Bits 10–8 This field selects the alternate function for GPIOB4.
Register Descriptions • • 0 = SS0 - QSPI0 Slave Select (default) 1 = SDA - I2C Serial Data 6.3.18.9 Reserved—Bit 1 This bit field is reserved. It must be set to 0. 6.3.18.10 Configure GPIOB0 (GPS_B0)—Bits 0 This field selects the alternate function for GPIOB0. • 0 = SCLK0 - QSPI0 Serial Clock (default) • 1 = SCL - I2C Serial Clock 6.3.19 SIM GPIO Peripheral Select Register 1 for GPIOB (SIM_GPSB1) See Section 6.3.16 for general information about GPIO Peripheral Select Registers.
6.3.19.6 Configure GPIOB9 (GPS_B9)—Bit 4 This field selects the alternate function for GPIOB9. • • 0 = SDA - I2C Serial Data (default) 1 = MSCANRX - MSCAN Receive Data 6.3.19.7 Reserved—Bit 3 This bit field is reserved. It must be set to 0. 6.3.19.8 Configure GPIOB8 (GPS_B8)—Bit 2 This field selects the alternate function for GPIOB8. • • 0 = SCL - I2C Serial Clock (default) 1 = MSCANTX - MSCAN Transmit Data 6.3.19.9 Reserved—Bit 1 This bit field is reserved. It must be set to 0. 6.3.19.
Register Descriptions 6.3.20.2 Configure GPIOD5 (GPS_D5)—Bit 12 This field selects the alternate function for GPIOD5. • • 0 = XTAL - External Crystal Oscillator Output (default) 1 = CLKIN - External Clock Input 6.3.20.3 Reserved—Bits 11–5 This bit field is reserved. Each bit must be set to 0. 6.3.20.4 Configure GPIOC12 (GPS_C12)—Bit 4 This field selects the alternate function for GPIOC12. • • 0 = ANB4 - ADCB, Channel 4 (default) 1 = RXD1 - QSCI1 Receive Data 6.3.20.
GPIOA5_PEREN Register SIM_GPSA0 Register GPIOA5 SIM_IPS0 Register PWM5 0 GPIOA5 pin 00 0 1 01 PWM FAULT2 Timer A3 10 1 Comparator A Output (Internal) Figure 6-24 Overall Control of Signal Source using SIM_IPSn Control IPSn settings should not be altered while an affected peripheral is in an enabled (operational) configuration. See the 56F802x and 56F803x Peripheral Reference Manual for details.
Register Descriptions 6.3.21.5 Reserved—Bits 10–9 This bit field is reserved. Each bit must be set to 0. 6.3.21.6 Select Peripheral Input Source for PWM4/PWM5 Pair Source (IPS0_PSRC2)—Bits 8–6 This field selects the alternate input source signal to feed PWM input PSRC2 as the PWM4/PWM5 pair source.
• • • 000 = I/O pin (External) - Use a PSRC0 input pin as PWM source (default) 001 = TA0 (Internal) - Use Timer A0 output as PWM source 010 = ADC SAMPLE0 (Internal) - Use ADC SAMPLE0 result as PWM source — If the ADC conversion result in SAMPLE0 is greater than the value programmed into the High Limit register HLMT0, then PWM0 is set to 0 and PWM1 is set to 1 — If the ADC conversion result in SAMPLE0 is less than the value programmed into the Low Limit register LLMT0, then PWM0 is set to 1 and PWM1 is set
Register Descriptions 6.3.22.4 Select Peripheral Input Source for SYNC Input to DAC 0 (IPS1_DSYNC0)—Bits 2–0 This field selects the alternate input source signal to feed DAC0 SYNC input.
6.3.23.5 Reserved—Bits 7–5 This bit field is reserved. Each bit must be set to 0. 6.3.23.6 Select Peripheral Input Source for TA1 (IPS2_TA1)—Bit 4 This field selects the alternate input source signal to feed Quad Timer A, input 1. • • 0 = I/O pin (External) - Use Timer A1 input/output pin 1 = CMPAO (Internal) - Use Comparator A output 6.3.23.7 Reserved—Bits 3–0 This bit field is reserved. Each bit must be set to 0.
Power-Saving Modes Table 6-2 Clock Operation in Power-Saving Modes Mode Core Clocks Peripheral Clocks Description Run Core and memory clocks enabled Peripheral clocks enabled Device is fully functional Wait Core and memory clocks disabled Peripheral clocks enabled Core executes WAIT instruction to enter this mode. Typically used for power-conscious applications. Possible recoveries from Wait mode to Run mode are: 1. Any interrupt 2.
possible to invoke Stop or Wait mode while in Standby mode for even greater levels of power reduction. A 400kHz external clock can optionally be used in Standby mode to produce the required Standby 200kHz system clock rate. Power-down mode, which selects the ROSC clock source but shuts it off, fully disables the device and minimizes its power utilization but is only recoverable via reset.
Clocks EXTENDED_POR JTAG POR Power-On Reset (active low) pulse shaper Delay 64 OSC_CLK Clock CLKGEN_RST Memory Subsystem OCCS COMBINED_RST External RESET IN (active low) pulse shaper COP_TOR (active low) SW Reset COP_LOR (active low) PERIP_RST Delay 32 OSC_CLK Clock RESET Delay 32 sys clocks pulse shaper Delay blocks assert immediately and deassert only after the programmed number of clock cycles.
The deassertion sequence of internal resets coordinates the device start up, including the clocking system start up. The sequence is described in the following steps: 1. As power is applied, the Relaxation Oscillator starts to operate. When a valid operating voltage is reached, the POR reset will release. 2. The release of POR reset permits operation of the POR reset extender. The POR extender generates an extended POR reset, which is released 64 OSC_CLK cycles after POR reset.
Interrupts Maximum Delay = 64 OSC_CLK cycles for POR reset extension and 32 OSC_CLK cycles for Combined reset extension RST MSTR_OSC Switch on falling OSC_CLK 96 MSTR_OSC cycles CKGEN_RST 2X SYS_CLK SYS_CLK SYS_CLK_D SYS_CLK_DIV2 32 SYS_CLK cycles delay Switch on falling SYS_CLK PERIP_RST Switch on falling SYS_CLK 32 SYS_CLK cycles delay CORE_RST Figure 6-29 Timing Relationships of Reset Signal to Clocks 6.8 Interrupts The SIM generates no interrupts.
program execution is otherwise unaffected. 7.2 Flash Access Lock and Unlock Mechanisms There are several methods that effectively lock or unlock the on-chip flash. 7.2.1 Disabling EOnCE Access On-chip flash can be read by issuing commands across the EOnCE port, which is the debug interface for the 56800E CPU. The TCK, TMS, TDO, and TDI pins comprise a JTAG interface onto which the EOnCE port functionality is mapped.
Product Analysis The user is responsible for directing the device to invoke the flash programming subroutine to reprogram the word $0000 into program memory location $00 7FF7. This is done by, for example, toggling a specific pin or downloading a user-defined key through serial interfaces. Note: Flash contents can only be programmed for 1s to 0s. 7.3 Product Analysis The recommended method of unsecuring a secured device for product analysis of field failures is via the method described in section 7.2.4.
Table 8-2 GPIO External Signals Map GPIO Function Peripheral Function LQFP Package Pin Notes GPIOA0 PWM0 56 Defaults to A0 GPIOA1 PWM1 55 Defaults to A1 GPIOA2 PWM2 47 Defaults to A2 GPIOA3 PWM3 48 Defaults to A3 GPIOA4 PWM4 / TA2 / FAULT1 43 SIM register SIM_GPS is used to select between PWM4, TA2, and FAULT1. Defaults to A4 GPIOA5 PWM5 / TA3 / FAULT2 39 SIM register SIM_GPS is used to select between PWM5, TA3, and FAULT2.
Configuration Table 8-2 GPIO External Signals Map (Continued) GPIO Function Peripheral Function LQFP Package Pin Notes GPIOB0 SCLK0 / SCL 42 SIM register SIM_GPS is used to select between SCLK and SCL. Defaults to B0 GPIOB1 SS0 / SDA 2 SIM register SIM_GPS is used to select between SS0 and SDA. Defaults to B1 GPIOB2 MISO0 / TA2 / PSRC0 33 SIM register SIM_GPS is used to select between MISO0, TA2, and PSRC0.
Table 8-2 GPIO External Signals Map (Continued) GPIO Function Peripheral Function LQFP Package Pin Notes GPIOB11 TB1 / CMPBO 60 SIM register SIM_GPS is used to select between TB1 and CMPBO. Defaults to B11 GPIOB12 CANTX 57 Defaults to B12 GPIOB13 CANRX 58 Defaults to B13 GPIOC0 ANA0 / CMPAI3 24 SIM register SIM_GPS is used to select between ANA0 and CMPAI3.
Reset Values Table 8-2 GPIO External Signals Map (Continued) GPIO Function Peripheral Function LQFP Package Pin Notes GPIOD2 TCK 29 Defaults to TCK GPIOD3 TMS 63 Defaults to TMS GPIOD4 EXTAL 53 Defaults to D4 GPIOD5 XTAL / CLKIN 52 SIM register SIM_GPSCD is used to select between XTAL and CLKIN. Defaults to D5 GPIOD6 DAC0 18 Defaults to D6 GPIOD7 DAC1 15 Defaults to D7 8.
Add. Offset Register Acronym $0 GPIOA_PUPEN $1 $2 $3 $4 $5 $6 $7 $8 $9 $A $B GPIOA_DATA GPIOA_DDIR GPIOA_PEREN GPIOA_IASSRT GPIOA_IEN GPIOA_IEPOL GPIOA_IPEND GPIOA_IEDGE GPIOA_PPOUTM GPIOA_RDATA GPIOA_DRIVE 15 R W RS 0 R W RS .0 0 0 R . 0.
Reset Values Add.
Add.
Reset Values Add.
Part 9 Joint Test Action Group (JTAG) 9.1 56F8037/56F8027 Information Please contact your Freescale sales representative or authorized distributor for device/package-specific BSDL information. The TRST pin is not available in this package. The pin is tied to VDD in the package. The JTAG state machine is reset during POR and can also be reset via a soft reset by holding TMS high for five rising edges of TCK, as described in the 56F802x and 56F803x Peripheral Reference Manual. Part 10 Specifications 10.
General Characteristics Table 10-1 Absolute Maximum Ratings (VSS = 0V, VSSA = 0V) Characteristic Symbol Notes Min Max Unit Supply Voltage Range VDD -0.3 4.0 V Analog Supply Voltage Range VDDA - 0.3 4.0 V ADC High Voltage Reference VREFHx - 0.3 4.0 V Voltage difference VDD to VDDA VDD - 0.3 0.3 V Voltage difference VSS to VSSA VSS - 0.3 0.3 V Digital Input Voltage Range VIN Pin Groups 1, 2 - 0.3 6.0 V Oscillator Voltage Range VOSC Pin Group 4 - 0.4 4.
10.1.
General Characteristics temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 7. See Section 12.1 for more details on thermal design considerations. Table 10-4 Recommended Operating Conditions (VREFL x= 0V, VSSA = 0V, VSS = 0V) Characteristic Symbol Min Typ Max Unit VDD, VDDA 3 3.3 3.6 V VREFHx 3.0 VDDA V Voltage difference VDD to VDDA VDD -0.1 0 0.1 V Voltage difference VSS to VSSA VSS -0.1 0 0.
10.2 DC Electrical Characteristics Table 10-5 DC Electrical Characteristics At Recommended Operating Conditions Symbol Notes Min Typ Max Unit Test Conditions Output Voltage High VOH Pin Group 1 2.4 — — V IOH = IOHmax Output Voltage Low VOL Pin Groups 1, 2 — — 0.4 V IOL = IOLmax Digital Input Current High (a) pull-up enabled or disabled IIH Pin Groups 1, 2 — 0 +/- 2.5 A VIN = 2.4V to 5.
DC Electrical Characteristics 2.0 0.0 µA - 2.0 - 4.0 - 6.0 - 8.0 - 10.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Volt Figure 10-1 IIN/IOZ vs. VIN (Typical; Pull-Up Disabled) Table 10-6 Current Consumption per Power Supply Pin Typical @ 3.3V, 25°C Mode Conditions Maximum@ 3.6V, 25°C IDD1 IDDA IDD1 IDDA RUN 32MHz Device Clock Relaxation Oscillator on PLL powered on Continuous MAC instructions with fetches from Program Flash All peripheral modules enabled.
Table 10-6 Current Consumption per Power Supply Pin (Continued) Typical @ 3.3V, 25°C Mode Conditions Maximum@ 3.
AC Electrical Characteristics measured directly on the VCAP pin. The specifications for this regulator are shown in Table 10-8. Table 10-8. Regulator Parameters Characteristic Short Circuit Current Short Circuit Tolerance (VCAP shorted to ground) Symbol Min Typical Max Unit ISS — 450 650 mA TRSC — — 30 minutes 10.3 AC Electrical Characteristics Tests are conducted using the input levels specified in Table 10-5.
10.4 Flash Memory Characteristics Table 10-9 Flash Timing Parameters Characteristic Symbol Min Typ Max Unit Program time1 Tprog 20 — 40 s Erase time 2 Terase 20 — — ms Tme 100 — — ms Mass erase time 1. There is additional overhead which is part of the programming sequence. See the 56F802x and 56F803x Peripheral Reference Manual for details. 2. Specifies page erase time. There are 512 bytes per page in the Program Flash memory. 10.
Phase Locked Loop Timing 10.6 Phase Locked Loop Timing Table 10-11 PLL Timing Characteristic Symbol Min Typ Max Unit External reference crystal frequency for the PLL1 fosc 4 8 — MHz Internal reference relaxation oscillator frequency for the PLL frosc — 8 — MHz PLL output frequency2 (24 x reference frequency) fop 96 192 — MHz PLL lock time3 tplls — 40 100 µs Accumulated jitter using an 8MHz external crystal as the PLL source4 JA — — 0.
8.16 8.08 MHz 8 7.92 7.84 -50 -25 0 25 50 75 100 125 150 175 Degrees C (Junction) Figure 10-5 Relaxation Oscillator Temperature Variation (Typical) After Trim 56F8037/56F8027 Data Sheet, Rev.
Reset, Stop, Wait, Mode Select, and Interrupt Timing 10.8 Reset, Stop, Wait, Mode Select, and Interrupt Timing Note: All address and data buses described here are internal.
10.
Serial Peripheral Interface (SPI) Timing SS SS is held High on master (Input) tC tR tF tCL SCLK (CPOL = 0) (Output) tCH tF tR tCL SCLK (CPOL = 1) (Output) tDH tCH tDS MISO (Input) MSB in tDI MOSI (Output) Master MSB out Bits 14–1 tDV Bits 14–1 tF LSB in tDI(ref) Master LSB out tR Figure 10-7 SPI Master Timing (CPHA = 0) 56F8037/56F8027 Data Sheet, Rev.
SS (Input) SS is held High on master tC tF tR tCL SCLK (CPOL = 0) (Output) tCH tF tCL SCLK (CPOL = 1) (Output) tCH tDS tR MISO (Input) MSB in tDI tDV(ref) MOSI (Output) Master MSB out tDH Bits 14–1 tDV Bits 14– 1 tF LSB in tDI(ref) Master LSB out tR Figure 10-8 SPI Master Timing (CPHA = 1) 56F8037/56F8027 Data Sheet, Rev.
Serial Peripheral Interface (SPI) Timing SS (Input) tC tF tCL SCLK (CPOL = 0) (Input) tCH tELD tCL SCLK (CPOL = 1) (Input) tCH tA MISO (Output) Slave MSB out tDV tDH MSB in tF tR Bits 14–1 tDS MOSI (Input) tELG tR Bits 14–1 tD Slave LSB out tDI tDI LSB in Figure 10-9 SPI Slave Timing (CPHA = 0) 56F8037/56F8027 Data Sheet, Rev.
SS (Input) tF tC tR tCL SCLK (CPOL = 0) (Input) tCH tELG tELD tCL SCLK (CPOL = 1) (Input) tDV tCH tR tA MISO (Output) tD tF Slave MSB out Bits 14–1 tDS tDV tDI tDH MOSI (Input) MSB in Slave LSB out Bits 14–1 LSB in Figure 10-10 SPI Slave Timing (CPHA = 1) 10.
Quad Timer Timing Timer Inputs PIN PINHL PINHL POUT POUTHL POUTHL Timer Outputs Figure 10-11 Timer Timing 56F8037/56F8027 Data Sheet, Rev.
10.11 Queued Serial Communication Interface (QSCI) Timing Table 10-16 QSCI Timing1 Characteristic Symbol Min Max Unit See Figure BR — (fMAX/16) Mbps — RXD3 Pulse Width RXDPW 0.965/BR 1.04/BR ns 10-12 TXD4 Pulse Width TXDPW 0.965/BR 1.
Freescale’s Scalable Controller Area Network (MSCAN) Timing 10.12 Freescale’s Scalable Controller Area Network (MSCAN) Timing Table 10-17 MSCAN Timing1 Characteristic Baud rate Bus wake-up detection Symbol Min Max Unit BRCAN — 1 Mbps TWAKEUP TIPBUS — µs 1. Parameters listed are guaranteed by design MSCAN_RX CAN receive data pin (Input) TWAKEUP Figure 10-14 Bus Wake-up Detection 10.
Table 10-18 I2C Timing (Continued) Characteristic Standard Mode Symbol Fast Mode Minimum Maximum Minimum Maximum Unit Set-up time for STOP condition tSU; STO 4.0 — 0.6 — s Bus free time between STOP and START condition tBUF 4.7 — 1.3 — s Pulse width of spikes that must be suppressed by the input filter tSP N/A N/A 0 50 ns 1. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL.
JTAG Timing 10.14 JTAG Timing Table 10-19 JTAG Timing Characteristic Symbol Min Max Unit See Figure TCK frequency of operation1 fOP DC SYS_CLK/8 MHz 10-16 TCK clock pulse width tPW 50 — ns 10-16 TMS, TDI data set-up time tDS 5 — ns 10-17 TMS, TDI data hold time tDH 5 — ns 10-17 TCK low to TDO data valid tDV — 30 ns 10-17 TCK low to TDO tri-state tTS — 30 ns 10-17 1. TCK frequency of operation must be less than 1/8 the processor rate.
10.15 Analog-to-Digital Converter (ADC) Parameters Table 10-20 ADC Parameters1 Parameter Symbol Min Typ Max Unit Resolution RES 12 — 12 Bits ADC internal clock fADIC 0.1 — 5.
Equivalent Circuit for ADC Inputs 10.16 Equivalent Circuit for ADC Inputs Figure 10-18 illustrates the ADC input circuit during sample and hold. S1 and S2 are always open/closed at the same time that S3 is closed/open. When S1/S2 are closed and S3 is open, one input of the sample and hold circuit moves to (VREFHx - VREFLx) / 2, while the other charges to the analog input voltage.
10.18 Digital-to-Analog Converter (DAC) Parameters Table 10-22 DAC Parameters Parameter Conditions/Comments Symbol Min Typ Max Unit 12 bits DC Specifications Resolution 12 Conversion time TBD — 2 µS Conversion rate TBD — 500.000 conv/sec tDAPU — — 11 µS Power-up time Time from release of PWRDWN signal until DACOUT signal is valid Accuracy Integral non-linearity1 Range of input digital words: 410 to 3891 ($19A - $F33) 5% to 95% of full range INL — +/- 3 +/- 8.
Power Consumption 10.19 Power Consumption See Section 10.1 for a list of IDD requirements for the 56F8037/56F8027. This section provides additional detail which can be used to optimize power consumption for a given application.
Because of the low duty cycle on most device pins, power dissipation due to capacitive loads was found to be fairly low when averaged over a period of time. E, the external [static component], reflects the effects of placing resistive loads on the outputs of the device. Sum the total of all V2/R or IV to arrive at the resistive load contribution to power. Assume V = 0.5 for the purposes of these rough calculations. For instance, if there is a total of eight PWM outputs driving 10mA into LEDs, then P = 8*.
56F8037/56F8027 Package and Pin-Out Information Part 11 Packaging 11.1 56F8037/56F8027 Package and Pin-Out Information VCAP VSS VDD GPIOD5 / XTAL / CLKIN GPIOD4 / EXTAL GPIOB8 / SCL / CANTX GPIOA1 / PWM1 GPIOA0 / PWM0 GPIOB12 / CANTX GPIOB13 / CANRX Orientation Mark GPIOB6 / RXD0 / SDA / CLKIN GPIOB1 / SS0 / SDA GPIOB11 / TB1 / CMPBO TDI / GPIOD0 GPIOC15 / ANB7 GPIOC14 / ANB6 TMS / GPIOD3 TDO / GPIOD1 This section contains package and pin-out information for the 56F8037/56F8027.
Table 11-1 56F8037/56F8027 64-Pin LQFP Package Identification by Pin Number1 Pin # Signal Name Pin # Signal Name Pin # Signal Name Pin # Signal Name 1 GPIOB6 RXD0 / SDA / CLKIN 17 VSSA 33 GPIOB2 MISO0 / TA2 / PSRC0 49 VCAP 2 GPIOB1 SS0 / SDA 18 GPIOD6 DAC0 34 GPIOA6 FAULT0 / TA0 50 VDD 3 GPIOB7 TXD0 / SCL 19 GPIOC3 ANA3 / VREFLA 35 GPIOA10 TB2 / CMPAI2 51 VSS 4 GPIOB5 TA1 / FAULT3 / CLKIN 20 GPIOC2 ANA2 / VREFHA 36 GPIOA8 FAULT1 / TA2 / CMPAI1 52 GPIOD5 XTAL / CLKIN 5
56F8037/56F8027 Package and Pin-Out Information 4X 4X 16 TIPS 0.2 H A-B D 0.2 C A-B D 64 A2 0.05 49 1 S (S) 48 q1 A 0.25 B q E E1 A1 3X E1/2 VIEW Y 16 E/2 L (L1) VIEW AA 32 NOTES: 1. DIMENSIONS AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE DATUM H IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS A, B AND D TO BE DETERMINED AT DATUM PLANE DATUM C.
Part 12 Design Considerations 12.1 Thermal Design Considerations An estimation of the chip junction temperature, TJ, can be obtained from the equation: TJ = TA + (RJ x PD) where: TA = Ambient temperature for the package (oC) RJ = Junction-to-ambient thermal resistance (oC/W) PD = Power dissipation in the package (W) The junction-to-ambient thermal resistance is an industry-standard value that provides a quick and easy estimation of thermal performance.
Electrical Design Considerations The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1mm of wire extending from the junction.
• Take special care to minimize noise levels on the VREF, VDDA, and VSSA pins • Using separate power planes for VDD and VDDA and separate ground planes for VSS and VSSA are recommended. Connect the separate analog and digital power and ground planes as close as possible to power supply outputs. If both analog circuit and digital circuit are powered by the same power supply, it is advisable to connect a small inductor or ferrite bead in serial with both VDDA and VSSA traces.
Electrical Design Considerations Part 14 Appendix Register acronyms are revised from previous device data sheets to provide a cleaner register description. A cross reference to legacy and revised acronyms are provided in the following table.
Table 14-1 Legacy and Revised Acronyms (Continued) Peripheral Reference Manual Data Sheet Register Name New Acronym Legacy Acronym New Acronym Legacy Acronym Processor Expert Acronym Memory Address Start End Inter-Integrated Circuit Interface (I2C) Module Control Register CTRL I2C_CTRL I2C_IBCR I2C_IBCR 0xF280 Target Address Register TAR IBCR I2C_TAR I2CTAR I2C_TAR 0xF282 Slave Address Register SAR I2C_SAR I2CSAR I2C_SAR 0xF242 Data Buffer & Command Register DATA I2C_DATA I2C_
Electrical Design Considerations Table 14-1 Legacy and Revised Acronyms (Continued) Peripheral Reference Manual Data Sheet Register Name New Acronym Clear Receive Done Interrupt Register Legacy Acronym New Acronym Legacy Acronym Processor Expert Acronym Memory Address Start End CLRRXDONE I2C_CLR_RXDONE I2C_CLR_RXDONE 0xF2AC CLRACT I2C_CLRACTIVITY I2C_CLRACTIVITY 0xF2AE Clear Stop Detect Interrupt Register CLRSTPDET I2C_CLR_STOPDET I2C_CLR_STOPDET 0xF2B0 Clear Start Detect Interrupt Re
Table 14-1 Legacy and Revised Acronyms (Continued) Peripheral Reference Manual Data Sheet Register Name Security Low Half Register New Acronym Legacy Acronym New Acronym Legacy Acronym SECLO FMSECL FM_SECLO FMSECL Processor Expert Acronym Memory Address Start End FMSECL 0xF404 Protection Register PROT FMPROT FM_PROT FMPROT FMPROT 0xF410 User Status Register USTAT FMUSTAT FM_USTAT FMUSTAT FMUSTAT 0xF413 Command Register CMD FMCMD FM_CMD FMCMD FMCMD 0xF414 Data Buffer Reg
Electrical Design Considerations Table 14-1 Legacy and Revised Acronyms (Continued) Peripheral Reference Manual Data Sheet Register Name New Acronym Legacy Acronym New Acronym Legacy Acronym Processor Expert Acronym Memory Address Start End Pulse Width Modulator (PWM) Module Control Register CTRL PMCTL Fault Control Register FCTRL Fault Status/Acknowledge Regis.
Table 14-1 Legacy and Revised Acronyms (Continued) Peripheral Reference Manual Data Sheet Register Name New Acronym Legacy Acronym New Acronym Legacy Acronym Processor Expert Acronym Memory Address Start End Transmitter Message Abort Acknowledge Register TAAK CAN_TAAK CANTAAK 0XF809 Transmitter FIFO Selection Register TBSEL CAN_TBSEL CANTBSEL 0XF80A Identifier Acceptance Control Register IDAC CAN_IDAC CANIDAC 0XF80B Miscellaneous Register MISC CAN_MISC CANMISC 0XF80D Receive Err
Electrical Design Considerations 56F8037/56F8027 Data Sheet, Rev.
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