Datasheet

Register Descriptions
56F8035/56F8025 Data Sheet, Rev. 6
Freescale Semiconductor 81
6.3 Register Descriptions
A write to an address without an associated register is an NOP. A read from an address without an
associated register returns unknown data.
Table 6-1 SIM Registers (SIM_BASE = $00 F100)
Register
Acronym
Base Address + Register Name
Section
Location
CTRL $0 Control Register 6.3.1
RSTAT $1 Reset Status Register 6.3.2
SWC0 $2 Software Control Register 0 6.3.3
SWC1 $3 Software Control Register 1 6.3.3
SWC2 $4 Software Control Register 2 6.3.3
SWC3 $5 Software Control Register 3 6.3.3
MSHID $6 Most Significant Half of JTAG ID 6.3.4
LSHID $7 Least Significant Half of JTAG ID 6.3.5
PWR $8 Power Control Register 6.3.6
Reserved
CLKOUT $A CLKO Select Register 6.3.7
PCR $B Peripheral Clock Rate Register 6.3.8
PCE0 $C Peripheral Clock Enable Register 0 6.3.9
PCE1 $D Peripheral Clock Enable Register 0 6.3.10
SD0 $E Stop Disable Register 0 6.3.11
SD1 $F Stop Disable Register 1 6.3.12
IOSAHI $10 I/O Short Address Location High Register 6.3.13
IOSALO $11 I/O Short Address Location Low Register 6.3.14
PROT $12 Protection Register 6.3.15
GPSA0 $13 GPIO Peripheral Select Register 0 for GPIOA 6.3.16
GPSA1 $14 GPIO Peripheral Select Register 1 for GPIOA 6.3.17
GPSB0 $15 GPIO Peripheral Select Register 0 for GPIOB 6.3.18
GPSB1 $16 GPIO Peripheral Select Register 1 for GPIOB 6.3.19
GPSCD $17 GPIO Peripheral Select Register for GPIOC and GPIOD 6.3.20
IPS0 $18 Internal Peripheral Source Select Register 0 for PWM 6.3.21
IPS1 $19 Internal Peripheral Source Select Register 1 for DACs 6.3.22
IPS2 $1A Internal Peripheral Source Select Register 2 for Quad Timer A 6.3.23
Reserved