Datasheet

Table Of Contents
56F8035/56F8025 Data Sheet, Rev. 6
80 Freescale Semiconductor
6.2 Features
The SIM has the following features:
Chip reset sequencing
Core and peripheral clock control and distribution
Stop/Wait mode control
System status control
Registers containing the JTAG ID of the chip
Controls for programmable peripheral and GPIO connections
Peripheral clocks for TMR and PWM with a high-speed (3X) option
Power-saving clock gating for peripherals
Three power modes (Run, Wait, Stop) to control power utilization
Stop mode shuts down the 56800E core, system clock, and peripheral clock
Wait mode shuts down the 56800E core and unnecessary system clock operation
Run mode supports full device operation
Controls the enable/disable functions of the 56800E core WAIT and STOP instructions with write protection
capability
Controls the enable/disable functions of Large Regulator Standby mode with write protection capability
Permits selected peripherals to run in Stop mode to generate Stop recovery interrupts
Controls for programmable peripheral and GPIO connections
Software chip reset
I/O short address base location control
Peripheral protection control to provide runaway code protection for safety-critical applications
Controls output of internal clock sources to CLKO pin
Four general-purpose software control registers are reset only at power-on
Peripherals Stop mode clocking control