Datasheet

56F8035/56F8025 Data Sheet, Rev. 6
78 Freescale Semiconductor
5.6.19.3 Vector Number - Vector Address Bus (VAB)—Bits 12–6
This read-only field shows bits [7:1] of the Vector Address Bus used at the time the last IRQ was taken.
In the case of a Fast Interrupt, it shows the lower address bits of the jump address. This field is only updated
when the 56800E core jumps to a new interrupt service routine.
Note: Nested interrupts may cause this field to be updated before the original interrupt service routine can
read it.
5.6.19.4 Interrupt Disable (INT_DIS)—Bit 5
This bit allows all interrupts to be disabled.
• 0 = Normal operation (default)
• 1 = All interrupts disabled
5.6.19.5 Reserved—Bits 4-2
This bit field is reserved. Each bit must be set to 1.
5.6.19.6 Reserved—Bits 1–0
This bit field is reserved. Each bit must be set to 0.
5.7 Resets
5.7.1 General
Table 5-4 Interrupt Priority Encoding
IPIC_VALUE[1:0]
Current Interrupt
Priority Level
Required Nested
Exception Priority
00 No interrupt or SWILP Priorities 0, 1, 2, 3
01 Priority 0 Priorities 1, 2, 3
10 Priority 1 Priorities 2, 3
11 Priority 2 or 3 Priority 3
Table 5-5 Reset Summary
Reset Priority
Source
Characteristics
Core Reset RST
Core reset from the SIM