Datasheet

Register Descriptions
56F8035/56F8025 Data Sheet, Rev. 6
Freescale Semiconductor 77
5.6.18 IRQ Pending Register 3 (IRQP3)
Figure 5-20 IRQ Pending Register 3 (IRQP3)
5.6.18.1 IRQ Pending (PENDING)—Bits 63–49
These register bit values represent the pending IRQs for interrupt vector numbers 49 through 63.
Ascending IRQ numbers correspond to ascending bit locations.
• 0 = IRQ pending for this vector number
• 1 = No IRQ pending for this vector number
5.6.19 Interrupt Control Register (ICTRL)
Figure 5-21 Interrupt Control Register (ICTRL)
5.6.19.1 Interrupt (INT)—Bit 15
This read-only bit reflects the state of the interrupt to the 56800E core.
• 0 = No interrupt is being sent to the 56800E core
• 1 = An interrupt is being sent to the 56800E core
5.6.19.2 Interrupt Priority Level (IPIC)—Bits 14–13
These read-only bits reflect the state of the new interrupt priority level bits being presented to the 56800E
core. These bits indicate the priority level needed for a new IRQ to interrupt the current interrupt being
sent to the 56800E core. This field is only updated when the 56800E core jumps to a new interrupt service
routine.
Note: Nested interrupts may cause this field to be updated before the original interrupt service routine can
read it.
• 00 = Required nested exception priority levels are 0, 1, 2, or 3
• 01 = Required nested exception priority levels are 1, 2, or 3
• 10 = Required nested exception priority levels are 2 or 3
• 11 = Required nested exception priority level is 3
Base + $11
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
PENDING[63:49]
Write
RESET
1111111111111111
$Base + $16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
INT IPIC VAB
INT_
DIS
1 1 1 0 0
Write
RESET
0000000000011100