Datasheet

Table Of Contents
Register Descriptions
56F8035/56F8025 Data Sheet, Rev. 6
Freescale Semiconductor 75
Interrupt vector is set to any other priority. A Fast Interrupt automatically becomes the highest priority
level 2 interrupt, regardless of its location in the interrupt table prior to being declared as Fast Interrupt.
Fast Interrupt 0 has priority over Fast Interrupt 1. To determine the vector number of each IRQ, refer to
the vector table.
5.6.13 Fast Interrupt 1 Vector Address Low Register (FIVAL1)
Figure 5-15 Fast Interrupt 1 Vector Address Low Register (FIVAL1)
5.6.13.1 Fast Interrupt 1 Vector Address Low (FIVAL1)—Bits 15–0
The lower 16 bits of the vector address used for Fast Interrupt 1. This register is combined with FIVAH1
to form the 21-bit vector address for Fast Interrupt 1 defined in the FIM1 register.
5.6.14 Fast Interrupt 1 Vector Address High (FIVAH1)
Figure 5-16 Fast Interrupt 1 Vector Address High Register (FIVAH1)
5.6.14.1 Reserved—Bits 15–5
This bit field is reserved. Each bit must be set to 0.
5.6.14.2 Fast Interrupt 1 Vector Address High (FIVAH1)—Bits 4–0
The upper five bits of the vector address used for Fast Interrupt 1. This register is combined with FIVAL1
to form the 21-bit vector address for Fast Interrupt 1 defined in the FIM1 register.
5.6.15 IRQ Pending Register 0 (IRQP0)
Figure 5-17 IRQ Pending Register 0 (IRQP0)
Base + $C
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
FAST INTERRUPT 1 VECTOR ADDRESS LOW
Write
RESET
0000000000000000
Base + $D
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
0 0 0 0 0 0 0 0 0 0 0
FAST INTERRUPT 1 VECTOR
ADDRESS HIGH
Write
RESET
0000000000000000
Base + $E
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read
PENDING[16:2] 1
Write
RESET
1111111111111111