Datasheet

Table Of Contents
56F8035/56F8025 Data Sheet, Rev. 6
54 Freescale Semiconductor
CMPB_FILT $2 Filter Register
Table 4-28 Queued Serial Communication Interface 0 Registers Address Map
(QSCI0_BASE = $00 F200)
Register Acronym Address Offset Register Description
QSCI0_RATE $0 Baud Rate Register
QSCI0_CTRL1 $1 Control Register 1
QSCI0_CTRL2 $2 Control Register 2
QSCI0_STAT $3 Status Register
QSCI0_DATA $4 Data Register
Table 4-29 Queued Serial Peripheral Interface 0 Registers Address Map
(QSPI0_BASE = $00 F220)
Register Acronym Address Offset Register Description
QSPI0_SCTRL $0 Status and Control Register
QSPI0_DSCTRL $1 Data Size and Control Register
QSPI0_DRCV $2 Data Receive Register
QSPI0_DXMIT $3 Data Transmit Register
QSPI0_FIFO $4 FIFO Control Register
QSPI0_DELAY $5 Delay Register
Table 4-30 I
2
C Registers Address Map
(I2C_BASE = $00 F280)
Register Acronym Address Offset Register Description
I2C_CTRL $0 Control Register
I2C_TAR $2 Target Address Register
I2C_SAR $4 Slave Address Register
I2C_DATA $8 RX/TX Data Buffer and Command Register
I2C_SSHCNT $A Standard Speed Clock SCL High Count Register
I2C_SSLCNT $C Standard Speed Clock SCL Low Count Register
I2C_FSHCNT $E Fast Speed Clock SCL High Count Register
I2C_FSLCNT $10 Fast Speed Clock SCL Low Count Register
I2C_ISTAT $16 Interrupt Status Register
I2C_IMASK $18 Interrupt Mask Register
Table 4-27 Comparator B Registers Address Map (Continued)
(CMPB_BASE = $00 F1F0)
Register Acronym Address Offset Register Description