Datasheet

Table Of Contents
56F8035/56F8025 Data Sheet, Rev. 6
48 Freescale Semiconductor
ITCN_IRQP0 $E IRQ Pending Register 0
ITCN_IRQP1 $F IRQ Pending Register 1
ITCN_IRQP2 $10 IRQ Pending Register 2
ITCN_IRQP3 $11 IRQ Pending Register 3
Reserved
ITCN_ICTRL $16 Interrupt Control Register
Reserved
Table 4-13 SIM Registers Address Map
(SIM_BASE = $00 F100)
Register Acronym Address Offset Register Description
SIM_CTRL $0 Control Register
SIM_RSTAT $1 Reset Status Register
SIM_SWC0 $2 Software Control Register 0
SIM_SWC1 $3 Software Control Register 1
SIM_SWC2 $4 Software Control Register 2
SIM_SWC3 $5 Software Control Register 3
SIM_MSHID $6 Most Significant Half JTAG ID
SIM_LSHID $7 Least Significant Half JTAG ID
SIM_PWR $8 Power Control Register
Reserved
SIM_CLKOUT $A Clock Out Select Register
SIM_PCR $B Peripheral Clock Rate Register
SIM_PCE0 $C Peripheral Clock Enable Register 0
SIM_PCE1 $D Peripheral Clock Enable Register 1
SIM_SD0 $E Peripheral STOP Disable Register 0
SIM_SD1 $F Peripheral STOP Disable Register 1
SIM_IOSAHI $10 I/O Short Address Location High Register
SIM_IOSALO $11 I/O Short Address Location Low Register
SIM_PROT $12 Protection Register
SIM_GPSA0 $13 GPIO Peripheral Select Register 0 for GPIOA
SIM_GPSA1 $14 GPIO Peripheral Select Register 1 for GPIOA
SIM_GPSB0 $15 GPIO Peripheral Select Register 0 for GPIOB
SIM_GPSB1 $16 GPIO Peripheral Select Register 1 for GPIOB
SIM_GPSCD $17 GPIO Peripheral Select Register for GPIOC and GPIOD
SIM_IPS0 $18 Internal Peripheral Source Select Register 0 for PWM
SIM_IPS1 $19 Internal Peripheral Source Select Register 1 for DACs
Table 4-12 Interrupt Control Registers Address Map (Continued)
(ITCN_BASE = $00 F0E0)
Register Acronym Address Offset Register Description