Datasheet
Table Of Contents
- Part 1 Overview
- Part 2 Signal/Connection Descriptions
- Part 3 OCCS
- Part 4 Memory Maps
- Part 5 Interrupt Controller (ITCN)
- 5.1 Introduction
- 5.2 Features
- 5.3 Functional Description
- 5.4 Block Diagram
- 5.5 Operating Modes
- 5.6 Register Descriptions
- 5.6.1 Interrupt Priority Register 0 (IPR0)
- 5.6.1.1 PLL Loss of Reference or Change in Lock Status Interrupt Priority Level (PLL IPL)-Bits 15-14
- 5.6.1.2 Low Voltage Detector Interrupt Priority Level (LVI IPL)-Bits 13-12
- 5.6.1.3 Reserved-Bits 11-10
- 5.6.1.4 EOnCE Receive Register Full Interrupt Priority Level (RX_REG IPL)- Bits 9-8
- 5.6.1.5 EOnCE Transmit Register Empty Interrupt Priority Level (TX_REG IPL)- Bits 7-6
- 5.6.1.6 EOnCE Trace Buffer Interrupt Priority Level (TRBUF IPL)- Bits 5-4
- 5.6.1.7 EOnCE Breakpoint Unit Interrupt Priority Level (BKPT_U IPL)- Bits 3-2
- 5.6.1.8 EOnCE Step Counter Interrupt Priority Level (STPCNT IPL)- Bits 1-0
- 5.6.2 Interrupt Priority Register 1 (IPR1)
- 5.6.2.1 GPIOD Interrupt Priority Level (GPIOD IPL)-Bits 15-14
- 5.6.2.2 Reserved-Bits 13-6
- 5.6.2.3 FM Command, Data, Address Buffers Empty Interrupt Priority Level (FM_CBE IPL)-Bits 5-4
- 5.6.2.4 FM Command Complete Interrupt Priority Level (FM_CC IPL)-Bits 3-2
- 5.6.2.5 FM Error Interrupt Priority Level (FM_ERR IPL)-Bits 1-0
- 5.6.3 Interrupt Priority Register 2 (IPR2)
- 5.6.3.1 QSCI 0 Transmitter Empty Interrupt Priority Level (QSCI0_XMIT IPL)- Bits 15-14
- 5.6.3.2 Reserved-Bits 13-10
- 5.6.3.3 QSPI 0 Transmitter Empty Interrupt Priority Level (QSPI0_XMIT IPL)- Bits 9-8
- 5.6.3.4 QSPI 0 Receiver Full Interrupt Priority Level (QSPI0_RCV IPL)-Bits 7-6
- 5.6.3.5 GPIOA Interrupt Priority Level (GPIOA IPL)-Bits 5-4
- 5.6.3.6 GPIOB Interrupt Priority Level (GPIOB IPL)-Bits 3-2
- 5.6.3.7 GPIOC Interrupt Priority Level (GPIOC IPL)-Bits 1-0
- 5.6.4 Interrupt Priority Register 3 (IPR3)
- 5.6.4.1 I2C Error Interrupt Priority Level (I2C_ERR IPL)-Bits 15-14
- 5.6.4.2 Reserved-Bits 13-6
- 5.6.4.3 QSCI 0 Receiver Full Interrupt Priority Level (QSCI0_RCV IPL)-Bits 5-4
- 5.6.4.4 QSCI 0 Receiver Error Interrupt Priority Level (QSCI0_RERR IPL)- Bits 3-2
- 5.6.4.5 QSCI 0 Transmitter Idle Interrupt Priority Level (QSCI0_TIDL IPL)- Bits 1-0
- 5.6.5 Interrupt Priority Register 4 (IPR4)
- 5.6.5.1 Timer A, Channel 3 Interrupt Priority Level (TMRA_3 IPL)- Bits 15-14
- 5.6.5.2 Timer A, Channel 2 Interrupt Priority Level (TMRA_2 IPL)- Bits 13-12
- 5.6.5.3 Timer A, Channel 1 Interrupt Priority Level (TMRA_1 IPL)- Bits 11-10
- 5.6.5.4 Timer A, Channel 0 Interrupt Priority Level (TMRA_0 IPL)- Bits 9-8
- 5.6.5.5 I2C Status Interrupt Priority Level (I2C_STAT IPL)-Bits 7-6
- 5.6.5.6 I2C Transmit Interrupt Priority Level (I2C_TX IPL)-Bits 5-4
- 5.6.5.7 I2C Receive Interrupt Priority Level (I2C_RX IPL)- Bits 3-2
- 5.6.5.8 I2C General Call Interrupt Priority Level (I2C_GEN IPL)-Bits 1-0
- 5.6.6 Interrupt Priority Register 5 (IPR5)
- 5.6.6.1 Programmable Interval Timer 1 Interrupt Priority Level (PIT1 IPL)- Bits 15-14
- 5.6.6.2 Programmable Interval Timer 0 Interrupt Priority Level (PIT0 IPL)- Bits 13-12
- 5.6.6.3 Comparator B Interrupt Priority Level (COMPB IPL)- Bits 11-10
- 5.6.6.4 Comparator A Interrupt Priority Level (COMPA IPL)- Bits 9-8
- 5.6.6.5 Reserved-Bits 7-0
- 5.6.7 Interrupt Priority Register 6 (IPR6)
- 5.6.7.1 Reserved-Bits 15-12
- 5.6.7.2 PWM Fault Interrupt Priority Level (PWM_F IPL)-Bits 11-10
- 5.6.7.3 Reload PWM Interrupt Priority Level (PWM_RL IPL)-Bits 9-8
- 5.6.7.4 ADC Zero Crossing Interrupt Priority Level (ADC_ZC IPL)-Bits 7-6
- 5.6.7.5 ADC B Conversion Complete Interrupt Priority Level (ADCB_CC IPL)-Bits 5-4
- 5.6.7.6 ADC A Conversion Complete Interrupt Priority Level (ADCA_CC IPL)-Bits 3-2
- 5.6.7.7 Programmable Interval Timer 2 Interrupt Priority Level (PIT2 IPL)-Bits 1-0
- 5.6.8 Vector Base Address Register (VBA)
- 5.6.9 Fast Interrupt Match 0 Register (FIM0)
- 5.6.10 Fast Interrupt 0 Vector Address Low Register (FIVAL0)
- 5.6.11 Fast Interrupt 0 Vector Address High Register (FIVAH0)
- 5.6.12 Fast Interrupt 1 Match Register (FIM1)
- 5.6.13 Fast Interrupt 1 Vector Address Low Register (FIVAL1)
- 5.6.14 Fast Interrupt 1 Vector Address High (FIVAH1)
- 5.6.15 IRQ Pending Register 0 (IRQP0)
- 5.6.16 IRQ Pending Register 1 (IRQP1)
- 5.6.17 IRQ Pending Register 2 (IRQP2)
- 5.6.18 IRQ Pending Register 3 (IRQP3)
- 5.6.19 Interrupt Control Register (ICTRL)
- 5.6.1 Interrupt Priority Register 0 (IPR0)
- 5.7 Resets
- Part 6 System Integration Module (SIM)
- 6.1 Introduction
- 6.2 Features
- 6.3 Register Descriptions
- 6.3.1 SIM Control Register (SIM_CTRL)
- 6.3.2 SIM Reset Status Register (SIM_RSTAT)
- 6.3.3 SIM Software Control Registers (SIM_SWC0, SIM_SWC1, SIM_SWC2, and SIM_SWC3)
- 6.3.4 Most Significant Half of JTAG ID (SIM_MSHID)
- 6.3.5 Least Significant Half of JTAG ID (SIM_LSHID)
- 6.3.6 SIM Power Control Register (SIM_PWR)
- 6.3.7 Clock Output Select Register (SIM_CLKOUT)
- 6.3.8 Peripheral Clock Rate Register (SIM_PCR)
- 6.3.9 Peripheral Clock Enable Register 0 (SIM_PCE0)
- 6.3.9.1 Comparator B Clock Enable (CMPB)-Bit 15
- 6.3.9.2 Comparator A Clock Enable (CMPA)-Bit 14
- 6.3.9.3 Digital-to-Analog Clock Enable 1 (DAC1)-Bit 13
- 6.3.9.4 Digital-to-Analog Clock Enable 0 (DAC0)-Bit 12
- 6.3.9.5 Reserved-Bit 11
- 6.3.9.6 Analog-to-Digital Converter Clock Enable (ADC)-Bit 10
- 6.3.9.7 Reserved-Bits 9-7
- 6.3.9.8 Inter-Integrated Circuit IPBus Clock Enable (I2C)-Bit 6
- 6.3.9.9 Reserved-Bit 5
- 6.3.9.10 QSCI 0 Clock Enable (QSCI0)-Bit 4
- 6.3.9.11 Reserved-Bit 3
- 6.3.9.12 QSPI 0 Clock Enable (QSPI0)-Bit 2
- 6.3.9.13 Reserved-Bit 1
- 6.3.9.14 PWM Clock Enable (PWM)-Bit 0
- 6.3.10 Peripheral Clock Enable Register 1 (SIM_PCE1)
- 6.3.10.1 Reserved-Bit 15
- 6.3.10.2 Programmable Interval Timer 2 Clock Enable (PIT2)-Bit 14
- 6.3.10.3 Programmable Interval Timer 1 Clock Enable (PIT1)-Bit 13
- 6.3.10.4 Programmable Interval Timer 0 Clock Enable (PIT0)-Bit 12
- 6.3.10.5 Reserved-Bits 11-4
- 6.3.10.6 Quad Timer A, Channel 3 Clock Enable (TA3)-Bit 3
- 6.3.10.7 Quad Timer A, Channel 2 Clock Enable (TA2)-Bit 2
- 6.3.10.8 Quad Timer A, Channel 1 Clock Enable (TA1)-Bit 1
- 6.3.10.9 Quad Timer A, Channel 0 Clock Enable (TA0)-Bit 0
- 6.3.11 Stop Disable Register 0 (SD0)
- 6.3.11.1 Comparator B Clock Stop Disable (CMPB_SD)-Bit 15
- 6.3.11.2 Comparator A Clock Stop Disable (CMPA_SD)-Bit 14
- 6.3.11.3 Digital-to-Analog Converter 1 Clock Stop Disable (DAC1_SD)-Bit 13
- 6.3.11.4 Digital-to-Analog Converter 0 Clock Stop Disable (DAC0_SD)-Bit 12
- 6.3.11.5 Reserved-Bit 11
- 6.3.11.6 Analog-to-Digital Converter Clock Stop Disable (ADC_SD)-Bit 10
- 6.3.11.7 Reserved-Bits 9-7
- 6.3.11.8 Inter-Integrated Circuit Clock Stop Disable (I2C_SD)-Bit 6
- 6.3.11.9 Reserved-Bit 5
- 6.3.11.10 QSCI0 Clock Stop Disable (QSCI0_SD)-Bit 4
- 6.3.11.11 Reserved-Bit 3
- 6.3.11.12 QSPI0 Clock Stop Disable (QSPI0_SD)-Bit 2
- 6.3.11.13 Reserved-Bit 1
- 6.3.11.14 PWM Clock Stop Disable (PWM_SD)-Bit 0
- 6.3.12 Stop Disable Register 1 (SD1)
- 6.3.12.1 Reserved-Bit 15
- 6.3.12.2 Programmable Interval Timer 2 Clock Stop Disable (PIT2_SD)-Bit 14
- 6.3.12.3 Programmable Interval Timer 1 Clock Stop Disable (PIT1_SD)-Bit 13
- 6.3.12.4 Programmable Interval Timer 0 Clock Stop Disable (PIT0_SD)-Bit 12
- 6.3.12.5 Reserved-Bits 11-4
- 6.3.12.6 Quad Timer A, Channel 3 Clock Stop Disable (TA3_SD)-Bit 3
- 6.3.12.7 Quad Timer A, Channel 2 Clock Stop Disable (TA2_SD)-Bit 2
- 6.3.12.8 Quad Timer A, Channel 1 Clock Stop Disable (TA1_SD)-Bit 1
- 6.3.12.9 Quad Timer A, Channel 0 Clock Stop Disable (TA0_SD)-Bit 0
- 6.3.13 I/O Short Address Location Register High (SIM_IOSAHI)
- 6.3.14 I/O Short Address Location Register Low (SIM_IOSALO)
- 6.3.15 Protection Register (SIM_PROT)
- 6.3.16 SIM GPIO Peripheral Select Register 0 for GPIOA (SIM_GPSA0)
- 6.3.17 SIM GPIO Peripheral Select Register 1 for GPIOA (SIM_GPSA1)
- 6.3.18 SIM GPIO Peripheral Select Register 0 for GPIOB (SIM_GPSB0)
- 6.3.18.1 Reserved-Bit 15
- 6.3.18.2 Configure GPIOB6 (GPS_B6)-Bits 14-13
- 6.3.18.3 Configure GPIOB5 (GPS_B5)-Bits 12-11
- 6.3.18.4 Reserved-Bits 10-8
- 6.3.18.5 Configure GPIOB3 (GPS_B3)-Bits 7-6
- 6.3.18.6 Configure GPIOB2 (GPS_B2)-Bits 5-4
- 6.3.18.7 Reserved-Bit 3
- 6.3.18.8 Configure GPIOB1 (GPS_B1)-Bit 2
- 6.3.18.9 Reserved-Bit 1
- 6.3.18.10 Configure GPIOB0 (GPS_B0)-Bits 0
- 6.3.19 SIM GPIO Peripheral Select Register 1 for GPIOB (SIM_GPSB1)
- 6.3.20 SIM GPIO Peripheral Select Register for GPIOC and GPIOD (SIM_GPSCD)
- 6.3.21 Internal Peripheral Source Select Register 0 for Pulse Width Modulator (SIM_IPS0)
- 6.3.21.1 Reserved-Bits 15-14
- 6.3.21.2 Select Peripheral Input Source for FAULT2 (IPS0_FAULT2)-Bit 13
- 6.3.21.3 Reserved-Bit 12
- 6.3.21.4 Select Input Source for FAULT1 (IPS0_FAULT1)-Bit 11
- 6.3.21.5 Reserved-Bits 10-9
- 6.3.21.6 Select Peripheral Input Source for PWM4/PWM5 Pair Source (IPS0_PSRC2)-Bits 8-6
- 6.3.21.7 Select Peripheral Input Source for PWM2/PWM3 Pair Source (IPS0_PSRC1)-Bits 5-3
- 6.3.21.8 Select Peripheral Input Source for PWM0/PWM1 Pair Source (IPS0_PSRC0)-Bits 2-0
- 6.3.22 Internal Peripheral Source Select Register 1 for Digital-to-Analog Converters (SIM_IPS1)
- 6.3.23 Internal Peripheral Source Select Register 2 for Quad Timer A (SIM_IPS2)
- 6.4 Clock Generation Overview
- 6.5 Power-Saving Modes
- 6.6 Resets
- 6.7 Clocks
- 6.8 Interrupts
- Part 7 Security Features
- Part 8 General-Purpose Input/Output (GPIO)
- Part 9 Joint Test Action Group (JTAG)
- Part 10 Specifications
- 10.1 General Characteristics
- 10.2 DC Electrical Characteristics
- 10.3 AC Electrical Characteristics
- 10.4 Flash Memory Characteristics
- 10.5 External Clock Operation Timing
- 10.6 Phase Locked Loop Timing
- 10.7 Relaxation Oscillator Timing
- 10.8 Reset, Stop, Wait, Mode Select, and Interrupt Timing
- 10.9 Serial Peripheral Interface (SPI) Timing
- 10.10 Quad Timer Timing
- 10.11 Serial Communication Interface (SCI) Timing
- 10.12 Inter-Integrated Circuit Interface (I2C) Timing
- 10.13 JTAG Timing
- 10.14 Analog-to-Digital Converter (ADC) Parameters
- 10.15 Equivalent Circuit for ADC Inputs
- 10.16 Comparator (CMP) Parameters
- 10.17 Digital-to-Analog Converter (DAC) Parameters
- 10.18 Power Consumption
- Part 11 Packaging
- Part 12 Design Considerations
- Part 13 Ordering Information
- Part 14 Appendix

56F8035/56F8025 Data Sheet, Rev. 6
34 Freescale Semiconductor
The 56F8000 family devices’ on-chip clock synthesis module has the following registers:
• Control Register (OCCS_CTRL)
• Divide-by Register (OCCS_DIVBY)
• Status Register (OCCS_STAT)
• Shutdown Register (OCCS_SHUTDN)
• Oscillator Control Register (OCCS_OCTRL)
For more information on these registers, please refer to the 56F802x and 56F803x Peripheral Reference
Manual.
3.4 Internal Clock Source
An internal relaxation oscillator can supply the reference frequency when an external frequency source or
crystal is not used. It is optimized for accuracy and programmability while providing several power-saving
configurations which accommodate different operating conditions. The internal relaxation oscillator has
very little temperature and voltage variability. To optimize power, the architecture supports a standby state
and a power-down state.
During a boot or reset sequence, the relaxation oscillator is enabled by default (the PRECS bit in the
PLLCR word is set to 0). Application code can then also switch to the external clock source and power
down the internal oscillator, if desired. If a changeover between internal and external clock sources is
required at power-on, the user must ensure that the clock source is not switched until the desired external
clock source is enabled and stable.
To compensate for variances in the device manufacturing process, the accuracy of the relaxation oscillator
can be incrementally adjusted to within + 0.078% of 8MHz by trimming an internal capacitor. Bits 0-9 of
the OSCTL (oscillator control) register allow the user to set in an additional offset (trim) to this preset
value to increase or decrease capacitance. Each unit added or subtracted changes the output frequency by
about 0.078% of 8MHz, allowing incremental adjustment until the desired frequency accuracy is achieved.
The center frequency of the internal oscillator is calibrated at the factory to 8MHz and the TRIM value is
stored in the Flash information block and loaded to the FMOPT1 register at reset. When using the
relaxation oscillator, the boot code should read the FMOPT1 register and set this value as OSCTL TRIM.
For further information, see the 56F802x and 56F803x Peripheral Reference Manual.
3.5 Crystal Oscillator
The internal crystal oscillator circuit is designed to interface with a parallel-resonant crystal resonator in a
frequency range of 4-8MHz, specified for the external crystal. Figure 3-1 shows a typical crystal oscillator
circuit. Follow the crystal supplier’s recommendations when selecting a crystal, since crystal parameters
determine the component values required to provide maximum stability and reliable start-up. The load
capacitance values used in the oscillator circuit design should include all stray layout capacitances. The
crystal and associated components should be mounted as near as possible to the EXTAL and XTAL pins
to minimize output distortion and start-up stabilization time.