Datasheet

Overview
56F8035/56F8025 Data Sheet, Rev. 6
Freescale Semiconductor 33
Part 3 OCCS
3.1 Overview
The On-Chip Clock Synthesis (OCCS) module allows designers using an internal relaxation oscillator, an
external crystal, or an external clock to run 56F8000 family devices at user-selectable frequencies up to
32MHz. For details, see the OCCS chapter in the 56F802x and 56F803x Peripheral Reference Manual.
3.2 Features
The OCCS module interfaces to the oscillator and PLL and offers these features:
• Internal relaxation oscillator
• Ability to power down the internal relaxation oscillator or crystal oscillator
• Ability to put the internal relaxation oscillator into Standby mode
• 3-bit postscaler provides control for the PLL output
• Ability to power down the PLL
• Provides a 2X system clock which operates at twice the system clock to the System Integration Module
(SIM)
• Provides a 3X system clock which operates at three times the system clock to PWM and Timer modules
• Safety shutdown feature is available if the PLL reference clock is lost
• Can be driven from an external clock source
The clock generation module provides the programming interface for the PLL, internal relaxation
oscillator, and crystal oscillator.
3.3 Operating Modes
In 56F8000 family devices, an internal oscillator, an external crystal, or an external clock source can be
used to provide a reference clock to the SIM.
The 2X system clock source output from the OCCS can be described by one of the following equations:
2X system frequency = oscillator frequency
2X system frequency = (oscillator frequency x 8) / (postscaler)
where:
postscaler = 1, 2, 4, 8, 16, or 32
The SIM is responsible for further dividing these frequencies by two, which will insure a 50% duty cycle
in the system clock output.